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參數(shù)資料
| 型號： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁數(shù)： | 4/84頁 |
| 文件大小： | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
4
REV. 1.0.0 2/4/03
General Description
The TMC22x5yA digital decoder can be used as a universal
input to digital video processing systems by decoding digital
composite video and transcoding digital component inputs
into a common data format.
The digital comb filter decoder implements one of sixteen
comb filter architectures to produce luminance and color dif-
ference component signals which are virtually free of the
cross-color and cross-luminance artifacts associated with
simple bandsplit filter decoders.
Table 1. TMC22x5yA Decoder Family
Because the cost/performance tradeoff varies among applica-
tions, the TMC22x5yA decoder has been developed as a
family of six parts. They are all assembled in the same
package, and fit the same footprint. The register maps are
identical.
Figure 1. Logic Symbol
The devices come in 8- and 10-bit resolution versions (see
Figure 2 for data alignment between 8- and 10-bit versions).
Within each resolution version there are three models, offer-
ing three-line adaptive comb filtering, two-line adaptive
comb filtering, and simple decoding. The TMC22153A
10-bit three-line comb filter can be programmed to emulate
any of the other parts. All prototyping can be performed with
this version to evaluate performance tradeoffs, and lower-
cost versions are easily substituted in production.
Input Processor
The digitized video and clocks provided to the decoder can
be either locked to the line frequency or the subcarrier fre-
quency of the digitized waveform, providing broadcast qual-
ity decoding from the NTSC square pixel rate of 12.27 MHz
to the PAL four times subcarrier pixel rate of 17.73 MHz.
Figure 2. Pixel Data Format
Inputs containing embedded GRS (Fairchild Video Input
Processors), TRS words (D1 multiplexed component sig-
nals), and TRS-ID words (deserialized D2 signals) can be
used to lock the internal horizontal and vertical state
machines to the embedded information. If this information is
not provided, external horizontal and vertical syncs are
required for all line-locked input formats, and are optional
for NTSC inputs locked to four times the subcarrier (4*Fsc).
A simple sync separator is provided for digitized inputs
locked to the subcarrier frequency: the internal sync separa-
tor locks to the mid point of syncs during the vertical field
group, then flywheels during the active portion of the field.
For this reason, the DHSYNC and DVSYNC operations are
not guaranteed in subcarrier mode.
Adaptive Comb Filter
The line based adaptive comb filter in the TMC22x5yA adds
or subtracts the high frequency data from three adjacent field
lines to produce the average of the high frequency luminance
by canceling the chrominance signals, which in flat fields of
color are 180 degrees apart. Unfortunately flat fields of color
are rare and, when vertical transitions in the picture occur,
the output of the comb filter contains a mixture of both high
frequency luminance and chrominance, at which time the
comb fails. To avoid the comb filter artifacts that occur when
this happens, three sets of error signals are sent to a user-pro-
grammable lookup table, allowing the output of the comb fil-
ter to be mixed with the output of an internal bandsplit
decoder.
To produce these comb fail error signals, the video on each
of the inputs to the comb filter is passed through a simple
bandsplit decoder. The low-frequency portion of the signal is
TMC2215yA
3
2
TMC2205yA
3
2
Function
1
1
10-bit Data
8-bit Data
D1 Interface
Line-Locked Mode
f
SC
-Locked Mode
Genlock Mode
NTSC Frame Comb
NTSC/PAL Field Comb
3-Line Comb
2-Line Comb
Line Grab
Pixel Grab
65-22x5yA-02
VIDEOA
9-0
VIDEOB
9-0
BUFFER
LDV
HSYNC
VSYNC
MASTER
TMC22x5yA
Multistandard
Digital
Video
Decoder
CLOCK
CS
R/W
D
7-0
A
1-0
G/Y
9-0
B/C
B9-0
R/C
R9-0
FID
2-0
AVOUT
DHSYNC
DVSYNC
SER
SET
RESET
SA
2-0
SDA
SCL
MSB
VA
9
VB
9
G/Y
9
B/C
B9
R/C
R9
LSB
VA
0
VB
0
G/Y
0
B/C
B0
R/C
R0
VA
8
VB
8
G/Y
8
B/C
B 8
R/C
R8
VA
2
VB
2
G/Y
2
B/C
B2
R/C
R2
VA
1
VB
1
G/Y
1
B/C
B1
R/C
R1
10 bit
VA
9
VB
9
G/Y
9
B/C
B9
R/C
R9
VA
8
VB
8
G/Y
8
B/C
B 8
R/C
R8
VA
2
VB
2
G/Y
2
B/C
B2
R/C
R2
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
8 bit
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