參數(shù)資料
型號(hào)： SII3114CTU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 69/127頁
文件大?。?/td> 564K
代理商： SII3114CTU
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
38
2007 Silicon Image, Inc.
EEPROM Memory Address – Command + Status
Address Offset: 98H
Access Type: Read/Write
Reset Value: 0x0800_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Mem
Error
M
e
m
Init
Done
M
e
m
Init
M
e
m
A
c
cess
St
art
Mem
Access
Type
Reserved
Mem Address
This register defines the address and command/status register for EEPROM memory interface in the SiI3114.
The register bits are also mapped to Base Address 5, Offset 58H. See “EEPROM Memory Address – Command +
Status” section on page 59 for bit definitions.
EEPROM Memory Data
Address Offset: 9CH
Access Type: Read/Write
Reset Value: 0x0000_00XX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for EEPROM memory interface in the SiI3114. The register bits are also
mapped to Base Address 5, Offset 5CH. See “EEPROM Memory Data” section on page 60 for bit definitions.
Channel 0/2 Task File Configuration + Status
Address Offset: A0H
Access Type: Read/Write
Reset Value: 0x6515_0101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
R
eserved
Watchdog
Int
Ena
Watchdog
Ena
Watchdog
Timeout
Interrupt
Status
V
irtua
lDMA
Int
IORDY
Monitoring
Reserved
Cha
nne
lRs
t
Buffe
re
d
Cmd
R
eserved
This register defines the task file configuration and status register for Channel 0/2 in the SiI3114. The register bits
are also mapped to Base Address 5, Offset A0H. See “Channel X Task File Configuration + Status” section on
page 65 for bit definitions.
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