參數(shù)資料
型號: SII3114CTU
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PQFP176
封裝: TQFP-176
文件頁數(shù): 103/127頁
文件大?。?/td> 564K
代理商: SII3114CTU
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
69
SiI-DS-0103-D
Serial ATA SError
Address Offset: 108H / 188H / 308H / 388H
Access Type: Read/Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
F
T
S
H
C
D
B W
I
N
RRRR
EP
CT
R
MI
DIAG
ERR
This register is the SError register as defined by the Serial ATA specification (section 10.1.2).
Bit [31:16]: DIAG – This field contains bits defined as shown in the following table. Writing a 1 to the
register bit clears the B, C, F, N, H, and W bits.
Table 25. SError Register Bits (DIAG Field)
Bit
Definition
Description
B
10b to 8b decode error
Latched decode error or disparity error from the Serial ATA PHY
C
CRC error
Latched CRC error from the Serial ATA PHY
D
Disparity error
N/A, always 0; this error condition is combined with the decode error and
reported as B error
F
Unrecognized FIS type
Latched Unrecognized FIS error from the Serial ATA Link
I
PHY Internal error
N/A, always 0
N
PHYRDY change
Indicates a change in the status of the Serial ATA PHY
H
Handshake error
Latched Handshake error from the Serial ATA PHY
R
Reserved
Always 0
S
Link Sequence error
N/A, always 0
T
Transport state transition error
N/A, always 0
W
ComWake
Latched ComWake status from the Serial ATA PHY
Bit [15:00]: ERR – This field contains bits defined as shown in the following table. The ERR Field is not
implemented; all bits are always 0.
Table 26. SError Register Bits (ERR Field)
Bit
Definition
Description
C
Non-recovered persistent Communication error or data integrity error
N/A, always 0
E
Internal Error
N/A, always 0
I
Recovered data Integrity error
N/A, always 0
M
Recovered communications error
N/A, always 0
P
Protocol error
N/A, always 0
R
Reserved
Always 0
T
Non-recovered Transient data integrity error
N/A, always 0
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