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| 型號(hào)： | SII3114CTU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 116/127頁(yè) |
| 文件大小： | 564K |
| 代理商： | SII3114CTU |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
81
SiI-DS-0103-D
with one additional step. Before the DMA is enabled, the Channel x Virtual DMA/PIO Read Ahead Byte
Count register must be written with the 32-bit count of the number of bytes to be transferred.
Wait for a PCI interrupt.
Read the DMA status bits [18:16] of the PCI Bus Master – Channel x register, and check that bit 18 is set
to make sure the interrupt was generated by the expected channel.
If expected channel interrupted, read bits [11:10] of the Channel x Task File Timing + Configuration +
Status register to determine the cause of the interrupt. Bit 11 is set if the ATA/ATAPI device has an
interrupt pending, bit 10 is set if a virtual DMA operation completed.
If a virtual DMA operation completed,
Write 00H to bits [7:0] of the PCI Bus Master – Channel x register to disable DMA operation.
Write 1 to bits [18:17] of the PCI Bus Master –Channel x register to reset the DMA status and
virtual DMA interrupt bits, and PCI interrupt.
Check the previously read DMA status bits to ensure the DMA completed successfully.
Because ATA/ATAPI commands that transfer data using PIO can generate several interrupts
during the data transfer phase of the command, a race condition is created between the interrupt
indicating the completion of a virtual DMA operation, and the interrupt from the ATA/ATAPI device
indicating it is ready to perform the next part of the data transfer. To prevent missing an
ATA/ATAPI device interrupt due to this race condition, it is necessary to re-read the Channel x
Task File Timing + Configuration + Status register after disabling DMA operation and examining
bit 11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the
steps below (assuming that the virtual DMA operation completed successfully).
If the ATA/ATAPI device has interrupted,
Read the device status at bits [31:24] in the Channel x Task File Register 1 register to clear the
device interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – Channel x register to clear the DMA Complete bit
(NOTE: The DMA Complete bit acts as a latched copy of the ATA interrupt line when the channel
is not performing a DMA operation).
If the ATA/ATAPI device is not reporting an error, and DRQ is asserted (bit 27 of Channel x Task
File Register 1), then the device is interrupting to transfer data to the device. To transfer the data,
the DMA registers are setup to only perform that part of the data transfer expected for this
interrupt. The DMA is setup similarly to the way it is when performing a normal write DMA
command, but with one additional step. Before the DMA is enabled, the Channel x Virtual
DMA/PIO Read Ahead Byte Count register must be written with the 32-bit count of the number of
bytes to be transferred for this interrupt.
Repeat the above steps starting at “Wait for PCI interrupt” until all data for the write command has been
transferred or an error has been detected.
Using Virtual DMA with DMA Capable Devices
Even though a device may be DMA capable, there are ATA/ATAPI commands that require that a PIO mode be
used to transfer data. For these commands, virtual DMA can be used to perform the data transfer. Using virtual
DMA with an ATA/ATAPI device that has already been configured to use DMA for normal read/write operation is
performed very much like the sequence described above for PIO mode only devices, but with the following
additional consideration: The Data Transfer Mode – Channel x register associated with the ATA/ATAPI device
needs to be programmed for a PIO type transfer mode before DMA operation is enabled, and must be re-
programmed with the DMA/UDMA transfer type used during normal DMA operation once the virtual DMA
operation is complete.
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