參數(shù)資料
型號： SII3114CTU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封裝： TQFP-176
文件頁數(shù)： 59/127頁
文件大?。?/td> 564K
代理商： SII3114CTU
SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
29
SiI-DS-0103-D
Base Address Register 0
Address Offset: 10H
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 0
001
This register defines the addressing of various control functions within the SiI3114. The register bits are defined
below.
Bit [31:03]: Base Address Register 0 (R/W). This register defines the I/O Space base address for Channel
0 task file registers.
Bit [02:00]: Base Address Register 0 (R). This bit field is not used and is hardwired to 001
B
Base Address Register 1
Address Offset: 14H
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 1
01
This register defines the addressing of various control functions within the SiI3114. The register bits are defined
below.
Bit [31:02]: Base Address Register 1 (R/W). This register defines the I/O Space base address for Channel
0 Device Control- Alternate Status register.
Bit [01:00]: Base Address Register 1 (R). This bit field is not used and is hardwired to 01
B.
Base Address Register 2
Address Offset: 18H
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 2
001
This register defines the addressing of various control functions within the SiI3114. The register bits are defined
below.
Bit [31:03]: Base Address Register 2 (R/W). This register defines the I/O Space base address for Channel
1 task file registers.
Bit [02:00]: Base Address Register 2 (R). This bit field is not used and is hardwired to 001
B.
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