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參數(shù)資料
| 型號(hào)： | SII3114CTU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 125/127頁 |
| 文件大小： | 564K |
| 代理商： | SII3114CTU |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2007 Silicon Image, Inc.
89
SiI-DS-0103-D
FIS Types Not Affiliated with Current ATA/ATAPI Operations
BIST Support
Far-End Retimed Loopback is supported in reception mode only. All other BIST codes will be rejected via R_ERR.
It defaults to be interlocked supported (for Far-End Retimed Loopback only).
The SiI3114 does not support any BIST in transmission mode. There is no provision to send the test patterns and
compare against loopback data.
BIST Signals
When SiI3114 enters the BIST operation, the “PHY offline” mode will be set in the DET bits of the Sstatus register.
This conditoin will remain asserted until the host generates an ATA reset (hreset_b asserted) or a COMINIT is
received from the device.
DMA Setup
DMA Setup FIS can only be sent as a transparent FIS. On Power up, DMA Setup FIS defaults to be rejected.
First Party DMA Read of Host Memory by Device
Sequence (FIS41cfg[1:0] = '10', i.e. interlocked):
Device sends DMA Setup FIS to host. The "D" field in the FIS is '0'.
The IntrlckFIS bit is set and causes an interrupt to the host.
The host driver checks the FIS type (RxFIS), sets up, and arms the DMA controller.
The host sets the DMAOutEn in the Serial ATA SMisc register.
The host sets the FPDMAWr in the Serial ATA SMisc register.
The host sets the Accept_FIS bit to accept the FIS.
The host sends one or more Data FISes. Note that no DMA Activate FIS is required for first party DMA.
There is no need to report transfer status.
The host clears the DMAOutEn when the transfer count is exhausted.
First Party DMA Write of Host Memory by Device
Sequence (FIS41cfg[1:0] = '10', i.e. interlocked):
Device sends DMA Setup FIS to host. The "D" field in the FIS is '1'.
The IntrlckFIS bit is set and causes an interrupt to the host.
The host driver checks the FIS type (RxFIS), sets up, and arms the DMA controller.
The host sets the DMAInEn in the Serial ATA SMisc register.
The host sets the Accept_FIS bit to accept the FIS.
The device sends one or more Data FISes.
There is no need to report transfer status.
The host clears the DMAInEn when the transfer count is exhausted
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