參數(shù)資料
型號(hào)： SII3114CTU
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 65/127頁(yè)
文件大?。?/td> 564K
代理商： SII3114CTU
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
34
2007 Silicon Image, Inc.
Power Management Control + Status
Address Offset: 64H
Access Type: Read/Write
Reset Value: 0x6400_4000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
PM
E
St
at
us
PPM
D
a
ta
Scale
PPM Data Sel
PM
E
Ena
Reserved
PPM
Power
St
at
e
This register defines the power management capabilities associated with the PCI bus. The register bits are
defined below.
Bit [31:24]: PPM Data (R) – PCI Power Management Data. This bit field is hardwired to 0x64.
Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [15]: PME Status (R) – PME Status. This bit is hardwired to 0. The SiI3114 does not support PME.
Bit [14:13]: PPM Data Scale (R) – PCI Power Management Data Scale. This bit field is hardwired to 10
B to
indicate a scaling factor of 10 mW.
Bit [12:09]: PPM Data Sel (R/W) – PCI Power Management Data Select. This bit field is set by the system
to indicate which data field is to be reported through the PPM Data bits (although current implementation
hardwires the PPM Data to indicate 1 Watt).
Bit [08]: PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3114 does not support PME.
Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: PPM Power State (R/W) – PCI Power Management Power State. This bit field is set by the
system to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3
(Hot).
PCI Bus Master – Channel 0/2
Address Offset: 70H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
PB
M
Simplex
P
B
M
DMA
Ca
p
1
P
B
M
DMA
Ca
p
0
R
eserved
DMA
Comp
PBM
Error
P
B
M
Ac
ti
v
e
Reserved
P
B
M
Rd-Wr
R
eserved
PB
M
Enable
This register defines the PCI bus master register for Channel 0/2 in the SiI3114. The register bits are also
mapped to Base Address 4, Offset 00H, Base Address 5, Offset 00H, and Base Address 5, Offset 10H (Note that
these registers are, however, not identical). See “PCI Bus Master – Channel X” section on page 53 for bit
definitions.
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