參數(shù)資料
型號(hào): SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁(yè)數(shù): 37/50頁(yè)
文件大?。?/td> 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
37 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
11. Dynamic characteristics
[1]
Applies to external clock, crystal oscillator max 24 MHz.
Table 26:
T
amb
=
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless otherwise specified.
Symbol Parameter
Dynamic characteristics
Conditions
V
CC
= 2.5 V
Min
10
V
CC
= 3.3 V
Min
V
CC
= 5.0 V
Min
Unit
Max
Max
Max
t
1w
, t
2w
f
XTAL
t
6s
t
6h
t
7d
t
7w
t
7h
t
9d
t
12d
t
12h
t
13d
t
13w
t
13h
t
15d
t
16s
t
16h
t
17d
t
18d
clock pulse duration
oscillator/clock frequency
address setup time
address hold time
IOR delay from chip select
IOR strobe width
chip select hold time from IOR
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
IOW strobe width
chip select hold time from IOW
write cycle delay
data setup time
data hold time
delay from IOW to output
delay to set interrupt from
Modem input
delay to reset interrupt from
IOR
delay from stop to set interrupt
-
48
-
-
-
-
-
-
90
15
-
-
-
-
-
-
100
100
6
-
0
0
10
26
0
20
-
-
10
20
0
25
15
5
-
-
-
80
-
-
-
-
-
-
26
15
-
-
-
-
-
-
33
24
6
-
80
-
-
-
-
-
-
23
15
-
-
-
-
-
-
29
23
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1] [2]
-
0
0
10
90
0
20
-
-
10
20
0
25
20
15
-
-
0
0
10
23
0
20
-
-
10
15
0
20
15
5
-
-
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
t
19d
25 pF load
-
100
-
24
-
23
ns
t
20d
-
1T
RCLK
[3]
-
1T
RCLK
[3]
-
1T
RCLK
[3]
ns
t
21d
delay from IOR to reset
interrupt
delay from start to set interrupt
delay from IOW to transmit
start
delay from IOW to reset
interrupt
delay from stop to set RXRDY
25 pF load
-
100
-
29
-
28
ns
t
22d
t
23d
-
8T
RCLK
[3]
100
24T
RCLK
[3]
-
8T
RCLK
[3]
45
24T
RCLK
[3]
-
8T
RCLK
[3]
40
24T
RCLK
[3]
ns
ns
t
24d
-
100
-
45
-
40
ns
t
25d
-
1T
RCLK
[3]
-
1T
RCLK
[3]
-
1T
RCLK
[3]
ns
t
26d
t
27d
t
28d
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset
TXRDY
RESET pulse width
baud rate divisor
-
-
-
100
100
8T
RCLK
[3]
-
-
-
45
45
8T
RCLK
[3]
-
-
-
40
40
8T
RCLK
[3]
ns
ns
ns
t
RESET
N
200
1
-
(2
16
1) 1
200
-
(2
16
1) 1
200
-
(2
16
1)
ns
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