參數(shù)資料
型號: SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁數(shù): 15/50頁
文件大?。?/td> 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
15 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.5 Interrupts
The SC16C754B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables each of the six types of
interrupts and the INT signal in response to an interrupt generation. The IER can also
disable the interrupt system by clearing bits 7:5 and 3:0. When an interrupt is generated,
the IIR indicates that an interrupt is pending and provides the type of interrupt through
IIR[5:0].
Table 6
summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
Table 6:
IIR[5:0]
Interrupt control functions
Priority
level
None
none
1
receiver line status
Interrupt type
Interrupt source
Interrupt reset method
00 0001
00 0110
none
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
none
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
read RHR
read RHR
00 1100
00 0100
2
2
RX time-out
RHR interrupt
stale data in RX FIFO
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
MSR[3:0] = 0
receive Xoff character(s)/special
character
RTS pin or CTS pin change state from
active (LOW) to inactive (HIGH)
00 0010
3
THR interrupt
read IIR
or
a write to the THR
00 0000
01 0000
4
5
modem status
Xoff interrupt
read MSR
receive Xon character(s)/Read of
IIR
read IIR
10 0000
6
CTS, RTS
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