參數(shù)資料
型號: SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁數(shù): 32/50頁
文件大?。?/td> 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
32 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.12 Transmission Control Register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control.
Table 20
shows Transmission Control Register bit
settings.
TCR trigger levels are available from 0 to 60 bytes with a granularity of four.
Remark:
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before Auto-RTS or software flow control is enabled to avoid spurious operation
of the device.
7.13 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4.
Table 21
shows Trigger Level Register bit settings.
Remark:
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 to 60 bytes
are available with a granularity of four. The TLR should be programmed for
N
4
, where N is
the desired trigger level.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
Table 20:
Bit
7:4
3:0
Transmission Control Register bits description
Symbol
Description
TCR[7:4]
RX FIFO trigger level to
resume
transmission (0-60).
TCR[3:0]
RX FIFO trigger level to
halt
transmission (0-60).
Table 21:
Bit
7:4
3:0
Trigger Level Register bits description
Symbol
Description
TLR[7:4]
RX FIFO trigger levels (4 to 60), number of characters available.
TLR[3:0]
TX FIFO trigger levels (4 to 60), number of spaces available.
Table 22:
Bit
7:4
FIFO ready register bits description
Symbol
Description
FIFO Rdy[7:4]
0 = there are less than a RX trigger level number of characters in the
RX FIFO
1 = the RX FIFO has more than a RX trigger level number of characters
available for reading
or
a time-out condition has occurred
FIFO Rdy[3:0]
0 = there are less than a TX trigger level number of spaces available in
the TX FIFO
1 = there are at least a TX trigger level number of spaces available in the
TX FIFO
3:0
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