參數(shù)資料
型號: SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁數(shù): 23/50頁
文件大小: 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
23 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Remark:
Refer to the notes under
Table 9
for more register access information.
7.1 Receiver Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled,
location zero of the FIFO is used to store the characters.
Remark:
In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
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