參數(shù)資料
型號: SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁數(shù): 27/50頁
文件大?。?/td> 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
27 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.6 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem.
Table 14
shows Modem Control Register bit settings.
[1]
MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
Table 14:
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
[1]
Clock select.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
MCR[6]
[1]
TCR and TLR enable.
logic 0 = no action
logic 1 = enable access to the TCR and TLR registers
MCR[5]
[1]
Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
MCR[4]
Enable loop-back.
logic 0 = normal operating mode
Logic 1 = enable local loop-back mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TX output is
looped back to the RX input internally.
MCR[3]
IRQ enable OP.
logic 0 = forces INTA-INTB outputs to the 3-state mode and OP output
to HIGH state
logic 1 = forces the INTA-INTB outputs to the active state and OP
output to LOW state. In loop-back mode, controls MSR[7].
MCR[2]
FIFO Ready enable.
logic 0 = disable the FIFO Rdy register
logic 1 = enable the FIFO Rdy register. In loop-back mode, controls
MSR[6].
MCR[1]
RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW).
In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the RTS
output is controlled by hardware flow control.
MCR[0]
DTR
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW).
In loop-back mode, controls MSR[5].
6
5
4
3
2
1
0
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