參數(shù)資料
型號: SC16C754B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5四異步/秒(最大)64字節(jié)的FIFO
文件頁數(shù): 19/50頁
文件大?。?/td> 259K
代理商: SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
19 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C754B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2
16
1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 13
. The output frequency of the baud rate generator is 16
×
the baud rate. The
formula for the divisor is:
Where:
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark:
The default value of prescaler after reset is divide-by-1.
Figure 13
shows the internal prescaler and baud rate generator circuitry.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark:
The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 7
and
Table 8
show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 14
shows the crystal clock circuit reference.
Fig 13. Prescaler and baud rate generator block diagram
divisor
XTAL1 crystal input frequency
prescaler
desired baud rate
---------------------------------------------------------------------------
--------------------------------------------------------------------------------
16
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
input clock
PRESCALER
LOGIC
(DIVIDE-BY-4)
reference
clock
internal
baud rate
clock for
transmitter
and receiver
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