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MFR4200 FlexRay Communication Controller
MFR4200 Data Sheet, Rev. 0
60
Freescale Semiconductor
3.2.3
Register Descriptions
A condensed overview of all registers is provided in
Section 3.2.2, “Register Map Summary
”
NOTE
All registers not shown in the CC memory map registers are not
implemented in hardware.
Any read operation on bits marked as ‘
Reserved
’ will return an
undefined value (either ‘1’ or ‘0’).
The host must take care that bits marked as ‘Reserved’ are set to 0 when
writing.
The reset value indicated for each register is the value that the register
has after a hard reset operation.
Meaning of the bit field character in the registers layout:
– ‘
r
’ indicates that the bit-field may be read by host
– ‘
w
’ denotes that the bit-field may be updated by host
– ‘
h
’ means that the bit-field is updated by the communication controller
RCVR
Rate Correction Value Register
32A
810
undefined
OCVR
Offset Correction Value Register
32C
812
undefined
EMCR
Even Measurement Counter Register
33C
828
undefined
OMCR
Odd Measurement Counter Register
33E
830
undefined
EMAnR
Even Measurement channel A n Register,
n=[0:15]
EMA0R=340
…
EMA15R=35E
EMA0R=832
…
EMA15R=862
undefined
EMBnR
Even Measurement channel B n Register,
n=[0:15]
EMB0R=360
…
EMB15R=37E
EMB0R=864
…
EMB15R=894
undefined
ESFIDnR
Even Sync ID n Register, n=[0:15]
EID0R=380
…
EID15R=39E
EID0R=896
…
EID15R=926
undefined
OMAnR
Odd Measurement channel A n Register,
n=[0:15]
OMA0R=3A0
…
OMA15R=3BE
OMA0R=928
…
OMA15R=958
undefined
OMBnR
Odd Measurement channel B n Register,
n=[0:15]
OMB0R=3C0
…
OMB15R=3DE
OMB0R=960
…
OMB15R=990
undefined
OSFIDnR
Odd Sync Frame ID n Register, n=[0:15]
OSFID0R=3E0
…
OSFID15R=3FE
OSFID0R=1008
…
OSFID15R=1022
undefined
Table 3-1. Register Map Summary
Register
Description
Address
(Hex)
Address
(Dec)
Hard Reset
(Hex)