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MFR4200 FlexRay Communication Controller
MFR4200 Data Sheet, Rev. 0
58
Freescale Semiconductor
CLR
Cycle Length Register
B2
178
undefined
MPCLR
Microticks per Cycle Low Register
B4
180
undefined
MPCHR
Microticks per Cycle High Register
B6
182
undefined
MCLDAR
Maximum Cycle Length Deviation Register
B8
184
undefined
TSSLR
Transmit Start Sequence Length Register
BA
186
undefined
SWCR
Symbol Window Configuration Register
BC
188
undefined
NITCR
Network Idle Time Configuration Register
BE
190
undefined
CSMR
Coldstart Maximum Register
C0
192
undefined
MSFR
Maximum Sync Frames Register
C2
194
undefined
LDTSR
Latest Dynamic Transmission Start Register
C4
196
undefined
MSLR
Minislot Length Register
C6
198
undefined
MSAPOR
Minislot Action Point Offset Register
C8
200
undefined
SSAPOR
Static Slot Action Point Offset Register
CA
202
undefined
MOCWCFR
Maximum Odd Cycles Without Clock
Correction Fatal Register
CC
204
undefined
DCAR
Delay Compensation Channel A Register
D0
208
undefined
DCBR
Delay Compensation Channel B Register
D2
210
undefined
LNLR
Listen timeout with Noise Length Register
D6
214
undefined
MOCWCPR
Maximum Odd Cycles Without clock
Correction Passive Register
D8
216
undefined
MOCR
Maximum Offset Correction Register
DA
218
undefined
MRCR
Maximum Rate Correction Register
DC
220
undefined
CDDR
Cluster Drift Damping Register
DE
222
undefined
SOCCTR
Start of Offset Correction Cycle Time
Register
E0
224
undefined
WUSTXIR
Wakeup Symbol TX Idle Register
EA
234
0
WUSTXLR
Wakeup Symbol TX Low Register
EC
236
0
SYNFAFMR
Sync Frame Acceptance Filter Mask
Register
EE
238
undefined
SYNFAFVR
Sync Frame Acceptance Filter Value
Register
F0
240
undefined
SYNFRFR
Sync Frame Rejection Filter Register
F2
242
undefined
EOCR
External Offset Correction Register
F4
244
undefined
ERCR
External Rate Correction Register
F6
246
undefined
Table 3-1. Register Map Summary
Register
Description
Address
(Hex)
Address
(Dec)
Hard Reset
(Hex)