![](http://datasheet.mmic.net.cn/370000/PFR4200MAE40_datasheet_16728610/PFR4200MAE40_119.png)
Memory Map and Registers
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
119
CDSTPNSIF — Coldstart Path Noise Interrupt Flag
This signal is set if the CC has entered startup via the coldstart noise path. This indicates that the CC tried
to start the network. If enabled, an interrupt remains pending while this flag is set.
1 – The startup has been entered via the coldstart noise path.
0 – The startup has not been entered via the coldstart noise path.
CDSTPNIF — Coldstart Path Normal Interrupt Flag
This signal is set if the CC has entered the startup via the normal coldstart path. This indicates that the CC
tried to start the network. If enabled, an interrupt is pending while this flag is set.
1 – Startup has been entered via the normal coldstart path.
0 – Startup has not been entered via the normal coldstart path.
3.2.3.6.8
Slot Status n Register with n = [0:7] (SSnR)
Address SS0R=0x74, SS1R=0x76, SS2R=0x78, SS3R=0x7A, SS4R=0x7C, SS5R=0x7E, SS6R=0x80, SS7R=0x82
Reset
0x0
Each of these registers holds the status of the slot specified in the corresponding slot status selection
register SSSnR for both channel A and channel B. The suffices “_A” and “_B” indicate whether the slot
status is valid for channel A or channel B, respectively. For a detailed description of the slot status flags,
refer to
Section 3.3.3, “Message Buffer Slot Status Vector
”.
The controller provides a pair of slot status registers for each monitored slot with the first register being
assigned to even communication cycles, and the second to odd communication cycles, as shown in
Table 3-8
.
The controller clears the slot status registers SSnR (see
Section 3.2.3.6.8, “Slot Status n Register with
n = [0:7] (SSnR)
”) when leaving the configuration state.
NOTE
Refer to
Table 3-4
for slot status monitoring availability in different
protocol states.
The slot status of slot n is updated within the first macrotick of slot n+1.
15
14
13
12
11
10
9
8
VCE_B
SYNCF_B
NULLF_B
SUPF_B
SERR_B
CERR_B
BVIOL_B
TXCON_B
rh
rh
rh
rh
rh
rh
rh
rh
7
6
5
4
3
2
1
0
VCE_A
SYNCF_A
NULLF_A
SUPF_A
SERR_A
CERR_A
BVIOL_A
TXCON_A
rh
rh
rh
rh
rh
rh
rh
rh
Figure 3-80. Slot Status n Register, n = [0:7]