![](http://datasheet.mmic.net.cn/370000/PFR4200MAE40_datasheet_16728610/PFR4200MAE40_105.png)
Memory Map and Registers
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
105
Slot status registers SSnR configured via slot status selection registers
SSSnR, as described in
Section 3.2.3.6.8, “Slot Status n Register with
n = [0:7] (SSnR)
” and
Section 3.2.3.5.6, “Slot Status Selection n
Register, n = [0:3] (SSSnR)
”.
Channel status error counters CSEC0R and CSEC1R, as described in
Section 3.2.3.5.4, “Channel Status Error Counter n Register, n = [0:1]
(CSECnR)
”.
Slot status information within message buffers, as described in
Section 3.3.3, “Message Buffer Slot Status Vector
”.
Slot status counter registers SSCnR configured via slot status counter
condition registers SSCCnR as described in
Section 3.2.3.5.7, “Slot
Status Counter n Register, n = [0:7] (SSCnR)
” and
Section 3.2.3.5.8,
“Slot Status Counter Condition n Register, n = [0:7] (SSCCnR)
”.
Refer to
Table 3-4
for slot status monitoring availability in different
protocol states.
3.2.3.5.8
Slot Status Counter Condition n Register, n = [0:7] (SSCCnR)
Address SSCC0R=0x5C, SSCC1R=0x5E, SSCC2R=0x60, SSCC3R=0x62, SSCC4R=0x64, SSCC5R=0x66, SSCC6R=0x68,
SSCC7R=0x6A
Reset
0x0
Each of these registers serves as condition to detect if the corresponding slot status counter (see
Section 3.2.3.5.7, “Slot Status Counter n Register, n = [0:7] (SSCnR)
”) is to be incremented.
SSCMx, x = [0:3] — Slot Status Mask
A binary AND operation is performed on this 4-bit vector and the status of each slot-channel tuple that is
not booked for transmission in the static part of the communication cycle.
If the result is 0, and conditions for null frame selection (NULLS), sync frame selection (SYNCS), startup
frame selection (SUPFS), and valid communication element selection (VCES) are not met, the counter will
not be incremented for that slot-channel tuple.
NULLFS — NULL Frame Selection
This register is used to restrict counting to received null frames only.
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
CHCFG1
CHCFG0
MULTCYC
r
r
r
r
r
rw
rw
rw
7
6
5
4
3
2
1
0
VCES
SYNCFS
NULLFS
SUPFS
SSCM3
SSCM2
SSCM1
SSCM0
rw
rw
rw
rw
rw
rw
rw
rw
Figure 3-70. Slot Status Counter Condition n Register, n = [0:7]