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參數(shù)資料
| 型號(hào)： | PFR4200MAE40 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | FlexRay Communication Controllers |
| 中文描述： | FlexRay通信控制器 |
| 文件頁(yè)數(shù)： | 188/260頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | PFR4200MAE40 |
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MFR4200 FlexRay Communication Controller
MFR4200 Data Sheet, Rev. 0
188
Freescale Semiconductor
To read a receive FIFO buffer, the host must lock the FIFO buffer by sending a lock request (LOCK=’1’)
to message buffer 0. When a FIFO buffer is locked (read back value of the LOCK=’1’), the message buffer
addressed by GETIDX appears in the active receive FIFO buffer. After reading, the FIFO buffer must be
unlocked, and the GETIDX pointer is incremented.
The complete set of FIFO acceptance/rejection filters consists of the following registers (see
Section 3.2.3.8, “Filtering Related Registers
”).
Two filter sets are available for FIFO filtering:
One FIFO acceptance filter set, comprising:
— FIFO acceptance filter message ID value register
— FIFO acceptance filter message ID mask register
One FIFO rejection filter set, comprising:
— FIFO rejection filter frame ID value register
— FIFO rejection filter frame ID mask register
The channels from which the received frame will be accepted or rejected by the FIFO
acceptance/rejection filters are specified in
Section 3.2.3.8.7, “FIFO Acceptance/Rejection Filter
Channel Register (FAFCHR)
”.
The FIFO acceptance filter value registers define the acceptable pattern of the frame to be received. The
FIFO acceptance filter mask registers specify which of the corresponding bits are marked ‘don’t care’ for
acceptance filtering.
The FIFO rejection filter value registers define the acceptable pattern of the frame to be rejected. The FIFO
rejection filter mask registers specify which of the corresponding bits are marked ‘don’t care’ for rejection
filtering.
If acceptance and rejection filter are configured to match the same identifier, the frame will be rejected.
NOTE
The content of the FIFO is not reset by entering, being in, or leaving the
configuration state. Therefore, if the CC has stored any messages in the
FIFO, and has entered the configuration state without reading those
messages, and has returned to normal operation, then those messages
will remain in the FIFO.
The CC automatically updates the BUFCSnR registers of the FIFO
buffers to 0x0 values when the CC enters the configuration state for the
first time.
The host must clear buffer control flags CFG, IFLG, and IENA (write
0x0000 to the buffer control register) of a message buffer that has
already been in use or that has already been configured, before the host
may extend the FIFO (alter the FIFO size) to include that message buffer
in the FIFO. Failing to do so will result in invalid indications in the
RBIVEC/TBIVEC registers (see
Section 3.2.3.6.1, “Receive Buffer
Interrupt Vector Register (RBIVECR)
” and
Section 3.2.3.6.2, “Transmit
Buffer Interrupt Vector Register (TBIVECR)
”), i.e. RBIVEC/TBIVEC
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| PFR4200MPB40 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:FlexRay Communication Controllers |
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