![](http://datasheet.mmic.net.cn/370000/PFR4200MAE40_datasheet_16728610/PFR4200MAE40_135.png)
Memory Map and Registers
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
135
3.2.3.8.3
Sync Frame Rejection Filter Register (SYNFRFR)
Address 0xF2
Reset
undefined state
If the ENSYNFF bit is set (see
Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)
”), this
register is used to identify a sync frame ID whose arrival time measurement values are to be rejected for
clock synchronization. Note that this register can be written at any time by the host, unlike SYNFAFMR
and SYNFAFVR (see
Section 3.2.3.8.2, “Sync Frame Acceptance Filter Mask Register (SYNFAFMR)
”
and
Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register (SYNFAFVR)
”).
NOTE
To ensure correct operation of the CC, the host should update this register
only during the NIT.
3.2.3.8.4
Cycle Counter Filter n Register, n = [0:58] (CCFnR)
Address CCF0R=0x202, CCF1R=0x206, …, CCF57R=0x2E6, CCF58R=0x2EA.
CCFnR=0x202 + 0x4*dec2hex(n)
Reset
undefined state
Each cycle counter filter register is related to an appropriate message buffer: CCF0R to message buffer 0,
CCF1R to message buffer 1, … , CCF58R to message buffer 58. (For more information, refer to
Section ,
“Receive, receive FIFO, and transmit message buffers are accessible to the host MCU only through the
active receive, active transmit, and active receive FIFO buffers.
”).
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
SYNFRF10
SYNFRF9
SYNFRF8
r
r
r
r
r
rw
rw
rw
7
6
5
4
3
2
1
0
SYNFRF7
SYNFRF6
SYNFRF5
SYNFRF4
SYNFRF3
SYNFRF2
SYNFRF1
SYNFRF0
rw
rw
rw
rw
rw
rw
rw
rw
Figure 3-108. Sync Frame Rejection Filter Register
15
14
13
12
11
10
9
8
Reserved
Reserved
CCM5
CCM4
CCM3
CCM2
CCM1
CCM0
r
r
rw*
rw*
rw*
rw*
rw*
rw*
7
6
5
4
3
2
1
0
Reserved
Reserved
CCV5
CCV4
CCV3
CCV2
CCV1
CCV0
r
r
rw*
rw*
rw*
rw*
rw*
rw*
Figure 3-109. Cycle Counter Filter n Register, n = [0:58]