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Message Buffer
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
147
NOTE
The CC indicates status information for transmit message buffers only,
in the TXCON bit; the remaining bits are used to indicated receive status
information. Therefore, if a message buffer is configured as a receive or
receive FIFO message buffer, its TXCON bit is not used by the CC. If a
message buffer is configured as a transmit message buffer, only its
TXCON bit is updated by the CC, while the remaining bits are not used
by the controller.
Refer to
Table 3-4
for slot status monitoring availability in different
protocol states.
After reception of a null frame or an invalid frame, the controller updates
only the slot status vector of a selected receive message buffer or FIFO
buffer. Other fields (see
Table 3-11
and
Table 3-12
) of those buffers stay
unaltered.
After reception of a valid frame, the controller updates the slot status
vector and the remainder of the receive message buffer or FIFO buffer.
After transmission of a frame, the controller updates the slot status
vector in the current transmit message buffer.
The controller updates a message buffer assigned to slot n within the first
macrotick of the slot n+1.
Empty static slots exhibit slot status 0x0000 on channel A and 0x0100
on channel B.
3.3.3.1
TXCON — TX Conflict
This flag indicates transmission conflicts, i.e. indicates that a reception is in progress when the controller
starts transmission. This bit indicates conflicts during transmission in static and dynamic segments.
0 – No transmission conflict detected.
1 – Transmission conflict detected.
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH
r
r
r
r
r
r
r
rh*
7
6
5
4
3
2
1
0
VCE
SYNCF
NULLF
SUPF
SERR
CERR
BVIOL
TXCON
rh*
rh*
rh*
rh*
rh*
rh*
rh*
r
Figure 3-120. Receive and Receive FIFO Message Buffer Slot Status Vector