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| 型號： | ORT8850 |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 70/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850 |
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70
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
In
Table 31, an input refers to a signal flowing into the embedded core and an output refers to a signal flowing out
of the embedded core.
Table 31. Embedded Core/FPGA Interface Signal Description
Pin Name
I/O
Description
STM or 8B/10B Signals
dinaa<7:0>
dinaa_par
dinaa_fp
dinab<7:0>
dinab_par
dinab_fp
dinac<7:0>
dinac_par
dinac_fp
dinad<7:0>
dinad_par
dinad_fp
dinba<7:0>
dinba_par
dinba_fp
dinbb<7:0>
dinbb_par
dinbb_fp
dinbc<7:0>
dinbc_par
dinbc_fp
dinbd<7:0>
dinbd_par
dinbd_fp
doutaa<7:0>
doutaa_par
doutaa_spe
doutaa_c1j1
doutaa_en
doutaa_fp
doutab<7:0>
doutab_par
doutab_spe
doutab_c1j1
doutab_en
doutab_fp
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Parallel bus of STM slice A, transmitter A. MSB is bit 7.
Parity for STM slice A, transmitter A.
Frame pulse or K control for STM slice A, transmitter A.
Parallel bus of STM slice A, transmitter B. MSB is bit 7.
Parity for STM slice A, transmitter B.
Frame pulse or K control for STM slice A, transmitter B.
Parallel bus of STM slice A, transmitter C. MSB is bit 7.
Parity for STM slice A, transmitter C.
Frame pulse or K control for STM slice A, transmitter C.
Parallel bus of STM slice A, transmitter D. MSB is bit 7.
Parity for STM slice A, transmitter D.
Frame pulse or K control for STM slice A, transmitter D.
Parallel bus of STM slice B, transmitter A. MSB is bit 7.
Parity for STM slice B, transmitter A.
Frame pulse or K control for STM slice B, transmitter A.
Parallel bus of STM slice B, transmitter B. MSB is bit 7.
Parity for STM slice B, transmitter B.
Frame pulse or K control for STM slice B, transmitter B.
Parallel bus of STM slice B, transmitter C. MSB is bit 7.
Parity for STM slice B, transmitter C.
Frame pulse or K control for STM slice B, transmitter C.
Parallel bus of STM slice B, transmitter D. MSB is bit 7.
Parity for STM slice B, transmitter D.
Frame pulse or K control for STM slice B, transmitter D.
Parallel bus of STM slice A, receiver A. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver A.
SPE signal for parallel bus of STM slice A, receiver A.
C1J1 signal for parallel bus of STM slice A, receiver A.
Enable for parallel bus of STM slice A, receiver A.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver A.
Parallel bus of STM slice A, receiver B. MSB is bit 7.
Parity for parallel bus of STM slice A, receiver B.
SPE signal for parallel bus of STM slice A, receiver B.
C1J1 signal for parallel bus of STM slice A, receiver B.
Enable for parallel bus of STM slice A, receiver B.
Frame pulse or COMMADET for parallel bus of STM slice A, receiver B.
O
O
O
O
O
O
O
O
O
O
O
O
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| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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