參數(shù)資料
型號： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 54/112頁
文件大?。?/td> 2417K
代理商： ORT8850
54
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
(continued)
Bit/Register Name(S)
Bit/
Register
Location
(Hex)
0xe0[6]
Register
Type
Reset
Value
(Hex)
Description
CDR control register 1
creg
0
Enables CDR test mode. Initiates CDR
’
s built-in self-
test:
0: Regular mode.
1: Test mode.
Enables bypassing of the 622 MHz clock synthesis
with TSTCLK.
0: Use PLL.
1: Bypass PLL (uses TSTCLK as reference clock).
Enables LVDS loopback.
0: No loopback.
1: Loopback.
When set to 1, controls bypass of 16 PLL generated
phases with 16 low-speed phases.
EN10BIT. Sets 10 to 1 MUX/deMUX:
1 = 10:1 MUX/deMUX.
0 = 8:1 MUX/deMUX.
0 = Long-haul I/F mode (enables CDR + STM opera-
tion).
1 = Short-haul I/F mode (disables CDR, enables Pi-
sched interfaces).
Enables 10-bit Ethernet word alignment per channel.
Used during internal built-in self-test mode:
0 = No loopback.
1 = Loopback.
Reserved bit (read-only):
0 = Shuts down Bidi logic and ignores auxiliary
bypass signals. Always set to 0.
Indicates minimum cell size and will be used to detect
cell underrun errors.
Indicates completion of the internal test. Only valid
when OTESTENB (0xf2[7] is high):
0 = Test running.
1 = Test complete.
Indicates success of the internal test. Valid only when
ITESTDONE is high:
0 = Test failed.
1 = Test passed.
Enables bypass of the PLL circuit. TSTCLK is used in
this mode.
1 = Enables internal self-test of the SHIM block. Both
internal and external loopback paths exist during this
test.
0xe0[5]
creg
0
0xe0[4]
creg
0
0xe0[3]
creg
0
CDR control register 1
0xe0[1]
creg
0
0xe0[0]
creg
0
CDR control register 4
Pi-Sched I/F Ctl register
0xe3[0:7]
0xf0[6]
creg
creg
0
0xf0[5]
creg
0
0xf0[0:4]
creg
Pi-Sched I/F status regis-
ter
0xf1[0]
sreg
0xf1[1]
sreg
Pi-Sched I/F Ctl register
0xf2[0]
creg
0
0xf2[1]
creg
0
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相關代理商/技術參數(shù)
參數(shù)描述
ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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