參數(shù)資料
型號： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 66/112頁
文件大小： 2417K
代理商： ORT8850
66
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary.
Table 30. FPSC Function Pin Description
* The V
SS
A_STM is combimed with V
SS
in packages that contain an internal V
SS
plane.
Symbol
I/O
Description
HSI LVDS Receive Pins
rxd_b_p0
rxd_b_n0
rxd_c_p0
rxd_c_n0
rxd_b_p1
rxd_b_n1
rxd_c_p1
rxd_c_n1
rxd_b_p2
rxd_b_n2
rxd_c_p2
rxd_c_n2
rxd_b_p3
rxd_b_n3
rxd_c_p3
rxd_c_n3
rxd_b_p4
rxd_b_n4
rxd_c_p4
rxd_c_n4
rxd_b_p5
rxd_b_n5
rxd_c_p5
rxd_c_n5
rxd_b_p6
rxd_b_n6
rxd_c_p6
rxd_c_n6
rxd_b_p7
rxd_b_n7
rxd_c_p7
rxd_c_n7
DAUTREC
V
DDA
_STM
V
SSA
_STM*
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVDS work link
—
channel AA (shared with
RapidIO
port B) .
LVDS work link
—
channel AA (shared with
RapidIO
port B).
LVDS protect link
—
channel AA (shared with
RapidIO
port C).
LVDS protect link
—
channel AA (shared with
RapidIO
port C).
LVDS work link
—
channel AB (shared with
RapidIO
port B).
LVDS work link
—
channel AB (shared with
RapidIO
port B).
LVDS protect link
—
channel AB (shared with
RapidIO
port C).
LVDS protect link
—
channel AB (shared with
RapidIO
port C).
LVDS work link
—
channel AC (shared with
RapidIO
port B).
LVDS work link
—
channel AC (shared with
RapidIO
port B).
LVDS protect link
—
channel AC (shared with
RapidIO
port C).
LVDS protect link
—
channel AC (shared with
RapidIO
port C).
LVDS work link
—
channel AD (shared with
RapidIO
port B).
LVDS work link
—
channel AD (shared with
RapidIO
port B).
LVDS protect link
—
channel AD (shared with
RapidIO
port C).
LVDS protect link
—
channel AD (shared with
RapidIO
port C).
LVDS work link
—
channel BA (shared with
RapidIO
port B).
LVDS work link
—
channel BA (shared with
RapidIO
port B).
LVDS protect link
—
channel BA (shared with
RapidIO
port C).
LVDS protect link
—
channel BA (shared with
RapidIO
port C).
LVDS work link
—
channel BB (shared with
RapidIO
port B).
LVDS work link
—
channel BB (shared with
RapidIO
port B).
LVDS protect link
—
channel BB (shared with
RapidIO
port C).
LVDS protect link
—
channel BB (shared with
RapidIO
port C).
LVDS work link
—
channel BC (shared with
RapidIO
port B).
LVDS work link
—
channel BC (shared with
RapidIO
port B).
LVDS protect link
—
channel BC (shared with
RapidIO
port C).
LVDS protect link
—
channel BC (shared with
RapidIO
port C).
LVDS work link
—
channel BD (shared with
RapidIO
port B).
LVDS work link
—
channel BD (shared with
RapidIO
port B).
LVDS protect link
—
channel BD (shared with
RapidIO
port C).
LVDS protect link
—
channel BD (shared with
RapidIO
port C).
Disable auto recovery for the PLL. Internal pull-down.
Analog V
DD
1.5 V power supply for the HSI block.
Analog V
SS
for the HSI block.
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ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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