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參數(shù)資料
| 型號(hào)： | ORT8850 |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 3/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850 |
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Agere Systems Inc.
3
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Table of Contents
(continued)
List of Figures
Page
List of Tables
Page
Figure 1. . ORCA ORT8850 Block Diagram .............13
Figure 2. . High-Level Diagram of ORT8850
Transceiver ............................................................14
Figure 3. . 8850 with 8B/10B Coding/Decoding ........18
Figure 4. . HSI Functional Block Diagram ................19
Figure 5. . Byte Ordering of Input/Output Interface
in STS-12 Mode .....................................................20
Figure 6. . SPE and C1J1 Functionality ....................26
Figure 7. . SPE Stuff Bytes .......................................27
Figure 8. . Interconnect of Streams for FIFO ............28
Figure 9. . Example of Inter-STM Alignment ............28
Figure 10. . Example of Intra-STM Alignment ..........28
Figure 11. . Example of Twin STS-12 Stream ..........28
Figure 12. . Examples of Link Alignment ..................29
Figure 13. . Pointer Mover State Machine ................32
Figure 14. . RapidIO Receive Cell Interface .............35
Figure 15. . RapidIO Transmit Cell Interface ............36
Figure 16. . Sample Power Supply Filter Network
for Analog HSI Power Supply Pins ........................56
Figure 17. . Receive Parallel Data/Control Timing ...58
Figure 18. . Transmit Parallel Data/Control Timing ..58
Figure 19. . ac Test Loads ........................................61
Figure 20. . Output Buffer Delays .............................61
Figure 21. . Input Buffer Delays ................................61
Figure 22. . LVDS Driver and Receiver and
Associated Internal Components ...........................62
Figure 23. . LVDS Driver and Receiver ....................62
Figure 24. . LVDS Driver ..........................................62
Figure 25. . Package Parasitics ..............................106
Table 1. .
ORCA
ORT8850 Family
—
Available FPGA Logic ................................................1
Table 2. . Transmitter TOH on LVDS Output
(Transparent Mode) .................................................22
Table 3. . Transmitter TOH on LVDS Output
(TOH Insert Mode) ...................................................22
Table 4. . Receiver TOH (Output Parallel Bus) ...........25
Table 5. . SPE and C1J1 Functionality .......................26
Table 6. . Valid Special Characters .............................30
Table 7. . Valid Starting Positions for an STS-Mc .......31
Table 8. .
RapidIO
Signals to/from FPGA ...................37
Table 9. . Signals Used as Register Bits ....................38
Table 10. . Structural Register Elements ...................39
Table 11. . Memory Map .............................................40
Table 12. . Memory Map Descriptions .......................45
Table 13. . Absolute Maximum Ratings ......................55
Table 14. . Recommended Operating Conditions ......55
Table 15. . Absolute Maximum Ratings ......................57
Table 16. . Recommended Operating Conditions ......57
Table 17. . Receiver Specifications ............................57
Table 18. . Transmitter Specifications ........................57
Table 19. . Synthesizer Specifications ........................57
Table 20. . Parallel Receive Data/Control Timing .......58
Table 21. . Transmit Parallel Data/Control Timing ......58
Table 22. . Driver dc Data ...........................................59
Table 23. . Driver ac Data ...........................................59
Table 24. . Driver Power Consumption .......................59
Table 25. . Receiver ac Data ......................................60
Table 26. . Receiver Power Consumption ..................60
Table 27. . Receiver dc Data ......................................60
Table 28. . LVDS Operating Parameters ....................60
Table 29. . FPGA Common-Function
Pin
Description
........................................................63
Table 30. . FPSC Function Pin Description ................66
Table 31. . Embedded Core/FPGA Interface
Signal Description ....................................................70
Table 32. . ORT8850H Pins That Are Unused in
ORT8850L ...............................................................77
Table 33. . ORT8850L 352-Pin PBGA Pinout .............78
Table 34. . ORT8850L and ORT8850H
680-Pin PBGAM Pinout ...........................................88
Table 35. .
ORCA
ORT8850 Plastic Package
Thermal Guidelines ...............................................106
Table 36. .
ORCA
ORT8850 Package Parasitics .....106
Table 37. . Device Type Options ..............................110
Table 38. . Temperature Options ..............................110
Table 39. . Package Type Options ...........................110
Table 40. .
ORCA
FPSC Package Matrix
(Speed Grades) .....................................................110
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| ORT8850H | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850L | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| OS1001 | Interface IC |
| OS1010 | Optoelectronic |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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