參數(shù)資料
型號： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 48/112頁
文件大?。?/td> 2417K
代理商： ORT8850
48
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
(continued)
Bit/Register Name(S)
Bit/
Register
Location
(Hex)
Register
Type
Reset
Value
(Hex)
Description
Channel Register Blocks
rx behavior in lof
force ais-l control
20, 38, 50,
68,
80, 98, b0,
c8 [0]
20, 38, 50,
68,
80, 98, b0,
c8 [1]
20, 38, 50,
68,
80, 98, b0,
c8 [2]
20, 38, 50,
68, 80, 98,
b0, c8 [3]
20, 38, 50,
68, 80, 98,
b0, c8 [4]
20, 38, 50,
68, 80, 98,
b0, c8 [5]
—
1
0
TOH serial output port par err
ins cmd
—
0
rx k1/k2 source select
—
0
parallel output bus parity err
ins cmd
—
0
channel enable/disable control
hi-z control of parallel output
bus
hi-z control of TOH data output
20, 38, 50,
68, 80, 98,
b0, c8 [6]
20, 38, 50,
68, 80, 98,
b0, c8 [7]
creg
creg
creg
0
0
0
rx behavior in log
0
When Rx direction OOF occurs, do not insert
AIS-L.
1
When Rx direction OOF occurs, insert AIS-L.
force ais-l control
0
Do not force AIS-L.
1
Force AIS-L.
0
Do not insert a parity error.
1
Insert parity error in parity bit of receive TOH serial output for
as long as this bit is set.
0
Set receive direction K2 K2 bytes to 0.
1
Pass receive direction K1 K2 though pointer mover.
0
Do not insert parity error.
1
Insert parity error in the parity bit of receive direction parallel
output bus for as long as this bit is set.
channel
enable / dis-
able control
0
Power down CDR channels (PWR_DN_A/B/C/
D_N=0). TOH_EN_A(or B, C, D)=0, and
DOUTA(or B, C, D)=0, can be used to 3-state out-
put buses.
1
Functional mode.
hi-z control of
parallel output
bus
0
DOUTA(or B, C, D) _EN=0, can be used to 3-state
output bus.
1
Functional mode.
hi-z control of
TOH data out-
put
0
TOH_EN_A(or B, C, D)=0, can be used to 3-state
TOH output lines.
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參數(shù)描述
ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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