參數(shù)資料
型號(hào)： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 68/112頁
文件大小： 2417K
代理商： ORT8850
68
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Table 30. FPSC Function Pin Description
(continued)
* The V
SS
A_shim is combimed with V
SS
in packages that contain an internal V
SS
plane.
Symbol
I/O
Description
HSI Test Signals
tstclk
mreset
testrst
resettx
tstMUX[9:0]s
scan_tstmd
scan_en
tstsuftld
e_toggle
I
I
I
I
Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-down.
Test mode reset. Internal pull-down.
Resets receiver clock division counter. Internal pull-up.
Resets transmitter clock division counter. Internal pull-up.
Test mode output port.
Test mode enable. Must be tie-low for normal operation.
Scan test enable. Internal pull-up.
Internal pull-down.
Internal pull-down.
Internal pull-down.
Internal pull-down.
RapidIO
LVDS Interface Pins (Receiver)
rxd_a_p<7:0>
I
LVDS data for
RapidIO
, receiver port A.
rxd_a_n<7:0>
I
LVDS data for
RapidIO
, receiver port A.
rxsoc_a_p
I
LVDS start-of-cell for
RapidIO
, receiver port A.
rxsoc_a_n
I
LVDS start-of-cell for
RapidIO
, receiver port A.
rxclk_a_p
I
LVDS receive clock for
RapidIO
, receiver port A.
rxclk_a_n
I
LVDS receive clock for
RapidIO
, receiver port A.
lvctap_a<1:0>
—
LVDS input center tap (use 0.01 uF to GND) internal pull-up.
rxd_b_p<7:0>
I
LVDS data for
RapidIO
, receiver port B.
rxd_b_n<7:0>
I
LVDS data for
RapidIO
, receiver port B.
rxsoc_b_p
I
LVDS start-of-cell for
RapidIO
, receiver port B.
rxsoc_b_n
I
LVDS start-of-cell for
RapidIO
, receiver port B.
rxclk_b_p
I
LVDS receive clock for
RapidIO
, receiver port B.
rxclk_b_n
I
LVDS receive clock for
RapidIO
, receiver port B.
lvctap_b<4:0>
—
LVDS input center tap (use 0.01 μF to GND) internal pull-up.
rxd_c_p<7:0>
I
LVDS data for
RapidIO
, receiver port C.
rxd_c_n<7:0>
I
LVDS data for
RapidIO
, receiver port C.
rxsoc_c_p
I
LVDS start-of-cell for
RapidIO
, receiver port C.
rxsoc_c_n
I
LVDS start-of-cell for
RapidIO
, receiver port C.
rxclk_c_p
I
LVDS receive clock for
RapidIO
, receiver port C.
rxclk_c_n
I
LVDS receive clock for
RapidIO
, receiver port C.
lvctap_c<4:0>
—
LVDS input center tap (use 0.01 μF to GND) internal pull-up.
ref10
—
LVDS reference voltage: 1.0 V ± 3%.
ref14
—
LVDS reference voltage: 1.4 V ± 3%.
reshi
—
LVDS resistor high pin ( 100
in series with reslo).
reslo
—
LVDS resistor low pin ( 100
in series with reshi).
V
DD
A_shim
I
Analog V
DD
1.5 V power supply for the Rapid IO block.
V
SS
A_shim
I
Analog V
SS
for the Rapid IO block.
O
I
I
I
I
I
I
elsel
exdnup
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ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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