參數(shù)資料
型號(hào): ORT8850
英文描述: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場(chǎng)可編程系統(tǒng)芯片(促進(jìn)文化基金)8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù): 52/112頁(yè)
文件大?。?/td> 2417K
代理商: ORT8850
52
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
(continued)
Bit/Register Name(S)
Bit/Register
Location
(Hex)
2a, 42, 5a, 72,
8a, a2, ba, d2
[0:3]
Register
Type
Reset
Value
(Hex)
0
Description
AIS interrupt flags 12, 9, 6, 3
AIS interrupt flags 11, 8, 5,
2, 10, 7, 4, 1
enable/mask register 12, 9,
6, 3
enable/mask register 11, 8,
5, 2, 10, 7, 4, 1
2b, 43, 5b, 73,
8b, a3, bb, d3
[0:7]
2c, 44, 5c, 74,
8c, a4, bc, d4
[0:3]
2d, 45, 5d, 75,
8d, a5, bd, d5
[0:7]
2e, 46, 5e, 76,
8e, a6, be, d6
[0:3]
iareg
iareg
iereg
iereg
00
0
00
These are the AIS-P alarm flags. 1 if the
serial input stream contains AIS.
ES overflow flags 12, 9, 6, 3
ES overflow flags 11, 8, 5, 2,
10, 7, 4, 1
enable/mask register 12, 9,
6, 3
enable/mask register 11, 8,
5, 2, 10, 7, 4, 1
2f, 47, 5f, 77,
8f, a7, bf, d7
[0:7]
30, 48, 60, 78,
90, a8, b0, d8
[0:3]
31, 49, 61, 79,
91, a9, b1, d9
[0:7]
iareg
iareg
iereg
iereg
0
00
0
00
These are the elastic store overflow alarm
flags.
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