參數(shù)資料
型號: ORT8850
英文描述: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場可編程系統(tǒng)芯片(促進文化基金)8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù): 62/112頁
文件大?。?/td> 2417K
代理商: ORT8850
62
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100
differential impedance, as shown below. External resistors are
not required. The differential driver and receiver buffers include termination resistors inside the device package, as
shown in Figure 22 below.
5-8703(F)
Figure 22. LVDS Driver and Receiver and Associated Internal Components
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an
unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to
ground, the LVDS driver will not suffer permanent damage. Figure 23 illustrates the terms associated with LVDS
driver and receiver pairs.
5-8704(F)
Figure 23. LVDS Driver and Receiver
5-8705(F)
Figure 24. LVDS Driver
LVDS DRIVER
50
50
LVDS RECEIVER
CENTER TAP
DEVICE PINS
100
EXTERNAL
V
GPD
V
OA
V
OB
V
IA
V
IB
A
B
AA
BB
DRIVER
INTERCONNECT
RECEIVER
V
OA
A
V
OB
B
C
A
C
B
R
LOAD
V
OD
= (V
OA
V
OB
)
V
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