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| 型號： | ORCAORT82G5 |
| 英文描述： | 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進文化基金 |
| 文件頁數(shù)： | 60/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT82G5 |
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ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
60
L Lucent Technologies Inc.
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the user-
programmable I/Os are 3-stated and pulled-up with an internal resistor. If any FPGA function pin is not used (or not
bonded to package pin), it is also 3-stated and pulled-up after configuration.
Table 39
.
FPGA Common-Function Pin Description
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Symbol
I/O
Description
Dedicated Pins
V
DD
—
3.3 V power supply.
V
DD
2
—
2.5 V power supply
GND
—
Ground supply.
RESET
I
During configuration, RESET forces the restart of configuration and a pull-up is enabled.
After configuration, RESET can be used as an FPGA logic direct input, which causes all
PLC latches/FFs to be asynchronously set/reset.
CCLK
I/O
In the master and asynchronous peripheral modes, CCLK is an output, which strobes
configuration data in. In the slave or synchronous peripheral mode, CCLK is input syn-
chronous with the data on DIN or D[7:0]. In microprocessor mode, CCLK is used inter-
nally and output for daisy-chain operation.
DONE
I
As an input, a low level on DONE delays FPGA start-up after configuration.*
O
As an active-high, open-drain output, a high level on this signal indicates that configura-
tion is complete. DONE has a permanent pull-up resistor.
PRGM
I
PRGM is an active-low input that forces the restart of configuration and resets the bound-
ary-scan circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high. This
pin always has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option, a
high-to-low transition on RD_CFG will initiate readback of the configuration data, includ-
ing PFU output states, starting with frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configu-
ration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins
M0, M1, M2
I
During powerup and initialization, M0, M1, and M2 are used to select the configuration
mode with their values latched on the rising edge off INIT. During configuration, a pull-up
is enabled. After configuration, these pins cannot be user-programmable
I/Os.
M3
I
During powerup and initialization, M3 is used to select the speed of the internal oscillator
during configuration with their values latched on the rising edge of
INIT
. When M3 is low,
the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During
configuration, a pull-up is enabled.
I/O
After configuration, this pin is a user-programmable I/O pin.*
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