參數(shù)資料
型號： ORCAORT82G5
英文描述： 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù)： 59/90頁
文件大小： 1915K
代理商： ORCAORT82G5
Lucent Technologies Inc.
Lucent Technologies Inc.
59
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Estimating Power Dissipation
The total operating power dissipated is estimated by summing the FPGA standby (I
DDSB
), internal, and external
power dissipated, in addition to the embedded block power.
Table 38. Embedded Block Power Dissipation
Note: Power is calculated assuming an activity factor of 20%.
The following discussion relates to the FPGA portion of the device. The internal and external power is the power
consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The
total operating power is as follows:
P
T
=
Σ
P
PLC
+
Σ
P
PIC
The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output
power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two:
P
PFU
= 0.078 mW/MHz
For each PFU output that switches, 0.136 mW/MHz needs to be multiplied times the frequency (in MHz) that the
output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor;
for example, 20%.
The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/
clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power
from the subset of those PFUs that are configured as synchronous memory. Therefore, the clock power can be cal-
culated for the four parts using the following equations:
ORT4622 Clock Power
P = [0.22 mW/MHz
+ (0.39 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit) ORT4622 clock power = 4.8 mW/MHz
The power dissipated in a PIC is the sum of the power dissipated in the four PIOs in the PIC. This consists of power
dissipated by inputs and ac power dissipated by outputs. The power dissipated in each PIO depends on whether it
is configured as an input, output, or input/output. If a PIO is operating as an output, then there is a power dissipa-
tion component for P
IN
, as well as P
OUT
. This is because the output feeds back to the input.
The power dissipated by an input buffer is (V
IH =
V
DD
–
0.3 V or higher)
estimated as:
P
IN
= 0.09 mW/MHz
The ac power dissipation from an output or bidirectional is estimated by the following:
P
OUT
= (C
L
+ 8.8 pF)
×
V
DD2
×
F Watts
where the unit for C
L
is farads, and the unit for F is Hz.
Number of Active Channels
Operating
Frequency (Hz)
Estimated Power Dissipated (Watt)
Min
—
—
—
—
Max
1.08
1.43
1.73
2.01
1 channel
2 channels
3 channels
4 channels
622
622
622
622
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