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參數(shù)資料
| 型號： | ORCAORT82G5 |
| 英文描述： | 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進文化基金 |
| 文件頁數(shù)： | 21/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORCAORT82G5 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
21
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description
(continued)
5-8584 (F)
Figure 7. Examples of Link Alignment
Pointer Mover Block (Backplane -> FPGA)
The pointer mover maps incoming frames to the line framing that is supplied by the FPGA logic. The K1/K2 bytes
and H1-SS bits are also passed through to the pointer generator so that the FPGA can receive them. The pointer
mover handles both concatenations inside the STS-12, and to other STS-12s inside the core.
The pointer mover block can correctly process any length of concatenation of STS frames (multiple of three) as
long as it begins on an STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) and is contained within the
smaller of STS-3, 12, or 48. See details in Table 5.
Table 5. Valid Starting Positions for an STS-Mc
STS-1
Number
STS-3cSPE
STS-6cSPE
STS-9cSPE
STS-12cSPE
STS-15cSPE
STS-18c to
STS-48c
SPEs
YES
—
—
—
—
—
—
—
—
—
—
NO
NO
NO
NO
NO
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
YES
YES
YES
NO
YES
YES
YES
NO
YES
YES
YES
NO
YES
YES
NO
NO
YES
YES
NO
NO
YES
YES
NO
NO
YES
YES
NO
NO
YES
NO
NO
NO
YES
NO
NO
NO
YES
NO
NO
NO
YES
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
Note: YES = STS-Mc SPE can start in that STS-1.
NO = STS-Mc SPE cannot start in that STS-1.
— = YES or NO, depending on the particular value of M.
24-byte
FIFO
24-byte
FIFO
ALL FPs
ARRIVE
TOGETHER
(WRITING
BEGINS)
12 CLOCKS
SYNC. PULSE
(READING
BEGINS)
SYNC. PULSE
(READING
BEGINS)
LAST FP
ARRIVES
4 CLOCKS
FIRST FP
ARRIVES
(WRITING
BEGINS)
10 CLOCKS
PERFECTLY ALIGNED FRAMES
4-byte SPREAD IN ARRIVING FRAMES
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