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| 型號： | ORCAORT82G5 |
| 英文描述： | 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC |
| 中文描述： | 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進文化基金 |
| 文件頁數(shù)： | 31/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORCAORT82G5 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
31
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map
(continued)
Table 10. Memory Map Bit Descriptions
Bit/Register
Name(s
)
Bit/
Register
Location
(hex)
Register
Type
Default
Value
(hex)
Description
Generic Register Block
fixed rev [7:0]
fixed ID LSB [7:0]
fixed ID MSB [7:0]
scratch pad [7:0]
00 [7:0]
01 [7:0]
02 [7:0]
03 [7:0]
sreg
01
01
A0
00
—
creg
The scratch pad has no function and is not used anywhere in the
ORT4622 core. However, this register can be written to and read from.
In order to write to registers in memory locations 06 to 7F, lockreg MSB
and lockreg LSB must be respectively set to the values of A0 and 01. If
the MSB and LSB lockreg values are not set to {A0, 01}, then any values
written to the registers in memory locations 06 to 7F will be ignored.
After reset (both hard and soft), the ORT4622 core is in a write locked
mode. The ORT4622 core needs to be unlocked before it can be written
to. Also note that the scratch pad register (03) can always be written to
since it is unaffected by write lock mode.
The FIFO alignment and global reset commands are both accessed via
the pulse register in memory address 06. The FIFO alignment command
is used to frame align the outputs of the four receive stm stream FIFOs.
The global reset command is a soft (software initiated) reset. Neverthe-
less, the global reset command will have the exact reset effect as a hard
(RST_N pin) reset.
lockreg MSB [7:0]
lockreg LSB [7:0]
04 [7:0]
05 [7:0]
creg
00
00
FIFO alignment
command
global reset
command
06 [0]
06 [1]
preg
NA
Device Register Block
LVDS loopback con-
trol
STS48 STS12 sel
08 [0]
creg
0
0
1
No loopback.
LVDS loopback, transmit to receive on.
This control signal is untracked in the ORT4622 core. It is a scratch bit,
and its value has no effect on the ORT4622 core.
ext
prot
sw
en
func
0
—
MUX is controlled by software (one control bit per MUX).
Output buffer 3-state signals are controlled by software (one
control bit per channel).
1
0
MUX on parallel output bus of channel A is controlled by
Prot_Switch A/B pin (0-> channel A, 1-> channel B).
MUX on parallel output bus of channel C is controlled by
Prot_Switch C/D pin (0 -> channel C, 1-> channel D).
Output buffer 3-state signals are controlled by software (one
control bit per channel).
1
1
MUX is controlled by software (one control bit per MUX).
Output buffer 3-state signals on parallel output bus of chan-
nels A and B are controlled by Prot_Switch A/B pin (0->
buffers active, 1-> hi-z).
Output buffer 3-state signals on parallel output bus of chan-
nels C and D are controlled by Prot_Switch C/D pin (0 ->
buffers active, 1-> hi-z).
08 [1]
creg
0
ext prot sw en
ext prot sw func
08 [3:2]
creg
0
ext
prot
sw
Switching control master.
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