參數(shù)資料
型號(hào)： ORCAORT82G5
英文描述： 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
中文描述： 1.0？.25/2.0？.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁(yè)數(shù)： 25/90頁(yè)
文件大?。?/td> 1915K
代理商： ORCAORT82G5
Lucent Technologies Inc.
25
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description
(continued)
5-9331
Notes: SPE signal behavior shown in this figure is just for illustration purposes: SPE behavior is dependent on pointer movements and concat-
enation.
SPE signal must be high during negative stuff opportunity byte time slots (H3) for which valid data is carried (negative stuffing).
SPE signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing).
Figure 10. SPE Stuff Bytes
STS-12
TOH ROW # 4
SPE ROW # 4
H1H1H1H1H1H1H1H1H1H1H1H1H2H2H2H2H2H2H2H2H2H2H2H2H3H3H3H3H3H3H3H3H3H3H3H3
STS-12
SPE
POSITIVE STUFF
OPPORTUNITY BYTES
1 2
3
4
5 6
7
8
9 10 11 12
NEGATIVE STUFF
OPPORTUNITY BYTES
SPE SIGNAL SHOWS NEGATIVE STUFFING FOR 2ND STS-1,
AND POSITIVE STUFFING FOR 6TH STS-1
Powerdown Mode
Powerdown mode will be entered when the corre-
sponding channel is disabled. Channels can be inde-
pendently enabled or disabled under software control.
Parallel data bus output enable and TOH serial data
output enable signals are made available to the FPGA
logic. The HSI macrocell’s corresponding channel is
also powered down. The device will power up with all
four channels in powerdown mode.
In addition, an LVDS_EN pin has been added to control
the LVDS pins during boundary scan. During functional
operation, enabling/disabling LVDS buffers is con-
trolled by software registers. When in boundary scan
mode, LVDS_EN controls the enabling/disabling of
LVDS buffers instead of software registers. This
LVDS_EN pin should be pulled high on the board for
functional operation, and pulled low during boundary
scan.
Redundancy and Protection Switching
The ORT4622 supports STS-12/STS-48 redundancy
by either software or hardware control for protection
switching applications. For the transmitter mode, no
additional functionality is required for redundant opera-
tion. For receiving data, STS-12 data redundancy can
be implemented within the same device, while STS-48
and above data stream requires a pair of ORT4622
devices to support redundancy.
In STS-12 mode, the channel A receive data bus port is
used for both channel A and channel B. Similarly, the
channel C receive data bus port is used for both chan-
nel C and channel D. Channel B and channel D
become the redundant channels. The channel B and
channel D receive data bus ports are unused. Soft reg-
isters provide independent control to the protection
switching MUXes for both parallel data ports and serial
TOH data ports. When direct hardware control for pro-
tection switching is needed, external protection switch
pins are available for channels A and B, and also chan-
nels C and D. The external protection switch pins only
support parallel SPE/TOH data protection switching,
but not the serial TOH data.
In STS-48 mode, two independent devices are
required to work and protect for redundancy. Parallel
and serial port output pins on the FPGA side should be
3-stated as the basis for supporting redundancy. The
existing local bus enable signals at the CIC can be
used as 3-state controls for FPGA data bus if needed,
which can be easily accessed by software control.
Users can also create their own protection switch 3-
state enable signals either in FPGA logic or external to
the device, depending on the specific application.
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