參數(shù)資料
型號: ORCAORT82G5
英文描述: 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
中文描述: 1.0?.25/2.0?.5/3.125 Gb /秒背板接口促進(jìn)文化基金
文件頁數(shù): 54/90頁
文件大?。?/td> 1915K
代理商: ORCAORT82G5
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
54
L Lucent Technologies Inc.
Timing Characteristics
(continued)
5-8611 (F)
Note: The CPU interface can be bit stream selected either from device I/O or FPGA interface. The timing diagram applies to both interfaces, but
not to the FPGA MPI block.
Figure 20. CPU Write Transaction
Table 36. Timing Requirements (CPU Write Transaction)
Symbol
T
PULSE
T
ADDR_MAX
Parameter
Min
5
Max
18
Unit
ns
ns
Minimum Pulse Width for CS_N
Maximum Time from Negative Edge
of CS_N to ADDR Valid
Maximum Time from Negative Edge
of CS_N to Data Valid
Maximum Time from Negative Edge
of CS_N to Negative Edge of RD_WR_N
Maximum Time from Negative Edge of CS_N to
Contents of Internal Register Latching DB[7:0]
Minimum Time Between a Write Cycle (falling
edge of CS_N) and Any Other Transaction
(read or write at falling edge of CS_N)
Maximum Time from Register FF to Pad
Minimum Hold Time that RD_WR_N,
ADDR and DB Must be Held Valid from
the Negative Edge of CS_N
T
DAT_MAX
25
ns
T
RD_WR_MAX
26
ns
T
WRITE_MAX
60
ns
T
ACCESS_MIN
60
ns
T
INT_MAX
T
RW_WR_N,
ADDR, DB_HOLD
57
20
ns
ns
DATA VALID
T
ACCESS_MIN
T
PULSE
OLD VALUE
NEW VALUE
T
WRITE_MAX
T
INT_MAX
T
ADDR_MAX
T
DAT_MAX RD_WR_MAX
CPU_CS_N
(CS_N)
CPU_RD_WR_N
(RD_WR_N)
CPU_ADDR[6:0]
(ADDR[6:0])
CPU_DATA[7:0]
(DB[7:0])
INTERNAL REGISTER
(SYS_CLK
DOMAIN)
CPU_INT_N
(INT_N)
T
RD_WR_N, ADDR_MAX, DB_HOLD
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