參數(shù)資料
型號(hào)： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁(yè)數(shù)： 62/160頁(yè)
文件大小： 1997K
代理商： OMAP5910(RISC)
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Functional Overview
50
August 2002 Revised August 2003
SPRS197B
The main features of the UART peripherals include:
Selectable UART/autobaud modes (autobauding on UART1 and UART2)
Dual 64-entry FIFOs for received and transmitted data payload
Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation
Programmable sleep mode
Complete status-reporting capabilities in both normal and sleep mode
Frequency prescaler values from 0 to 65535 to generate the appropriate baud rates
Interrupt request generated if multiple System DMA requests
Baud rate from 300 bits/s up to 1.5M bits/s
Autobauding between 1200 bits/s and 115.2K bits/s
Software/hardware flow control
Programmable XON/XOFF characters
Programmable auto-RTS and auto-CTS
Programmable serial interface characteristics
5-, 6-, 7-, or 8-bit characters
Even-, odd-, or no-parity bit generation and detection
1, 1.5, or 2 stop-bit generation
False start bit detection
Line break generation and detection
Fully prioritized interrupt system controls
Internal test and loopback capabilities
Modem control functions (CTS, RTS, DSR, DTR)
NOTE:
DSR and DTR are only available on UART1 and UART3.
The IrDA functions available on UART3 are as follows:
Slow infrared (SIR) operations
Framing error, cyclic redundancy check (CRC) error, abort pattern (SIR) detection
8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors
3.8.2 General-Purpose I/O (GPIO)
There are up to 14 shared GPIO pins on the OMAP5910 device which may be accessed and controlled by
either the DSP public peripheral bus or the MPU public peripheral bus. Each GPIO pin is independently
configurable to be used by either the DSP or MPU. The MPU controls which processor owns each GPIO pin
by configuring a pin control register that only the MPU can access.
Each GPIO pin can be used as either an input or output pin with GPIO inputs being synchronized internally
to a peripheral clock. GPIO inputs may also optionally be configured to generate an interrupt condition to the
processor which owns the GPIO pin. The sense of the interrupt condition is configurable such that either a
high-to-low or low-to-high transition causes the interrupt condition.
Some of the GPIO pins are multiplexed with other interface pins specific to other device peripherals. Refer
to Table 23 to decide which GPIO pins are multiplexed with other peripheral signals.
3.8.3 Mailbox Registers
Four sets of shared mailbox registers are available for communication between the DSP and MPU. These
registers are discussed further in Section 3.12, Interprocessor Communication.
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