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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁(yè)數(shù)： | 61/160頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Functional Overview
49
August 2002 Revised August 2003
SPRS197B
Because McBSP1 and McBSP3 do not have the CLKR and FSR pins available, the transmit clock and frame
sync pins (CLKX and FSX) must be used for bit clock and frame synchronization on both the transmit and
receive channels of these McBSPs.
The functional clock to McBSP1 and McBSP3 is fixed at the OMAP5910 base operating frequency (12 MHz
or 13 MHz). The bit-clock rate for these McBSPs is therefore limited to 6 or 6.5 MHz (one half the base
frequency).
Only McBSP1 has the CLKS pin available. If the sample rate generator (SRG) is used on McBSP1, the
reference clock to the SRG can be configured to be either an external reference provided on the CLKS pin,
or the internal base (12- or 13-MHz) device clock. However, if the SRG is used on McBSP3, the only reference
clock available to this SRG is the base device clock as clock reference.
3.7.2 Multichannel Serial Interface (MCSI)
The multichannel serial interface (MCSI) provides flexible serial interface with multichannel transmission
capability. The MCSI allows the DSP to access a variety of external devices, such as audio codecs and other
types of analog converters. The DSP public peripheral bus has access to two MCSIs: MCSI1 and MCSI2.
These MCSIs provide full-duplex transmission and master or slave clock control. All transmission parameters
are configurable to cover the maximum number of operating conditions. The MCSIs have the following
features:
Master or slave clock control (transmission clock and frame synchronization pulse)
Programmable transmission clock frequency (master mode) up to one half the OMAP5910 base
frequency (12 or 13 MHz)
Reception clock frequency (slave mode) of up to the base frequency (12 or 13 MHz)
Single-channel or multichannel (x16) frame structure
Programmable word length: 3 to 16 bits
Full-duplex transmission
Programmable frame configuration
Continuous or burst transmission
Normal or alternate framing
Normal or inverted frame and clock polarities
Short or long frame pulse
Programmable oversize frame length
Programmable frame length
Programmable interrupt occurrence time (TX and RX)
Error detection with interrupt generation on wrong frame length
System DMA support for both TX and RX data transfers
Shared Peripherals
3.8
The shared peripherals are connected to both the MPU Public Peripheral bus and the DSP Public Peripheral
bus. In the case of the UARTs, these connections are achieved via a TI Peripheral Bus Switch, which must
be configured to allow MPU or DSP access to the UARTs. The other shared peripherals have permanent
connections to both public peripheral buses, although read and write accesses to each peripheral register may
differ.
3.8.1 Universal Asynchronous Receiver/Transmitter (UART)
The OMAP5910 device has three Universal Asynchronous Receiver/Transmitter (UART) peripherals which
are accessible on the DSP public and MPU public peripheral buses. A TI peripheral bus switch configured by
the MPU allows either TIPB access to these UART peripherals. All three UARTs are standard
16C750-compatible UARTs implementing an asynchronous transfer protocol with various flow control options.
Two of the three UARTs (UART1 and UART2) have autobaud capability to automatically determine and adjust
to the baud rate of the external connected device. One of the UARTs (UART3) can function as a general UART
or can optionally function as an IrDA interface.
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