參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 138/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Electrical Specifications
126
August 2002 Revised August 2003
SPRS197B
Table 515. McBSP Switching Characteristics
§
NO.
PARAMETER
MIN
MAX
UNIT
M0
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
McBSP1
CLKR/X int
2
33
ns
M1
tc(CKRX)
tw(CKRXH)
tw(CKRXL)
Cycle time, CLKR/X
CLKR/X int
2P
ns
M2
Pulse duration, CLKR/X high
CLKR/X int
0.45D
0.55D
ns
M3
Pulse duration, CLKR/X low
CLKR/X int
0.45C
0.55C
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
McBSP2
CLKR int
1
13
ns
CLKR ext
3
24
ns
McBSP1
CLKX int
4
13
CLKX ext
7
39
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
McBSP2
CLKX int
1
4
ns
CLKX ext
2
24
McBSP3
CLKX int
1
9
CLKX ext
2
37
McBSP1
CLKX int
2
7
CLKX ext
7
40
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted
when in Data Delay 0 (XDATDLY=00b) mode.
McBSP2
CLKX int
0
10
ns
CLKX ext
3
27
McBSP3
CLKX int
1
10
CLKX ext
1
16
McBSP1
FSX int
28
Delay time, FSX high to DX valid
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
FSX ext
25
M9
td(FXH-DXV)
McBSP2
FSX int
30
ns
FSX ext
27
McBSP3
FSX int
FSX ext
10
27
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
§T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
Only DXENA=0 is supported for all OMAP5910 McBSPs.
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