參數(shù)資料
型號: OMAP5910(RISC)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 56/160頁
文件大小: 1997K
代理商: OMAP5910(RISC)
Functional Overview
44
August 2002 Revised August 2003
SPRS197B
The screen is intended to be mapped to the frame buffer as one contiguous block where each horizontal line
of pixels is mapped to a set of consecutive bytes of words in the frame memory.
The principle features of the LCD controller are:
Dedicated 64-entry x 16-bit FIFO
Dedicated LCD DMA channel for LCD
Programmable display including support for 2-, 4-, 8-, 12-, and 16-bit graphics modes
Programmable display resolutions up to 1024 pixels by 1024 lines (assuming sufficient system bandwidth)
Support for passive monochrome (STN) displays
Support for passive color (STN) displays
Support for active color (TFT) displays
Patented dithering algorithm, providing:
15 grayscale levels for monochrome passive displays
3375 colors for color passive displays
65536 colors for active color displays
256-entry x 12-bit palette
Programmable pixel rate
Pixel clock plus horizontal and vertical synchronization signals
ac-bias drive signal
Active display enable signal
256-entry x 12-bit palette
Dual-frame buffers
3.6
MPU Public Peripherals
Peripherals on the MPU Public Peripheral bus may only be accessed by the MPU and the System DMA
Controller, which is configured by the MPU. This bus is called a public bus because it is accessible by the
System DMA controller. The DSP cannot access peripherals on this bus.
3.6.1 USB Host Controller
The OMAP5910 USB host controller communicates with USB devices at the USB low-speed (1.5M-bit/s
maximum) and full-speed (12M-bit/s maximum) data rates. The controller is USB compliant. For additional
information, see the
Universal Serial Bus Specification, Revision 2.0
and the
OpenHCI – Open Host Controller
Interface Specification for USB, Release 1.0a
, hereafter called the OHCI Specification for USB.
The OMAP5910 USB host controller implements the register set and makes use of the memory data structures
which are defined in the OHCI Specification for USB. These registers and data structures are the mechanism
by which a USB host controller driver software package may control the OMAP5910 USB host controller.
The USB host controller is connected to the MPU public peripheral bus for MPU access to registers. The USB
host controller gains access to the data structures in system memory via the internal Local Bus interface. The
OMAP5910 device implements a variety of signal multiplexing options that allows use of the USB host
controller with any of the three available USB interfaces on the device. One of these interfaces utilizes an
integrated USB transceiver, while the other two require external transceivers. The host controller can support
up to three downstream ports.
The OMAP5910 USB host controller implementation does not implement every aspect of the functionality
defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting,
and the OHCI ownership change interrupt. Other restrictions are imposed by OMAP5910 system memory
addressing mechanisms and the effects of the OMAP5910 pin-multiplexing options.
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