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參數資料
| 型號： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁數： | 41/160頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Introduction
29
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
USB Miscellaneous Signals
USB.CLKO
W4
T3
USB clock output. 6-MHz divided clock output of the internal USB DPLL provided
for reference. Common for all USB host and Function peripherals.
O
USB.PUEN
W4
T3
USB pullup enable. Control output used in conjunction with an external pullup
resistor to implement USB device connect and disconnect via software.
USB.PUEN is used with the USB Function peripheral.
O
USB.VBUS
R18
M16
USB voltage bus enable. USB.VBUS is used to provide a logic-high voltage level
which may be used to enable pullup resistors on the USB bus to indicate
connection or disconnection status of the OMAP5910 device as a USB Function
device.
I
JTAG/Emulation Interface
TCK
W18
T14
IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with
a 50% duty cycle. The changes on the test access port (TAP) of input signals TDI
and TMS are clocked into the TAP controller, instruction register, or selected test
data register on the rising edge of TCK. Changes at the TAP output signal TDO
occur on the falling edge of TCK.
I
TDI
Y19
U17
IEEE Standard 1149.1 test data input. TDI is clocked into the selected register
(instruction or data) on the rising edge of TCK.
I
TDO
AA19
U16
IEEE Standard 1149.1 test data output. The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in
the high-impedance state except when the scanning of data is in progress.
O
TMS
V17
R13
IEEE Standard 1149.1 test mode select. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
I
TRST
Y18
U15
IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard
1149.1 scan system control of the operations of the device. If TRST is not
connected, or driven low, the device operates in its functional mode, and the IEEE
standard 1149.1 signals are ignored.
I
EMU0
V16
R17
Emulation pin 0. When TRST is driven high, EMU0 is used as an interrupt to or
from the emulator system and is defined as input/output by way of the IEEE
standard 1149.1 scan system.
I/O
EMU1
W17
T13
Emulation pin 1. When TRST is driven high, EMU1 is used as an interrupt to or
from the emulator system and is defined as input/output by way of the IEEE
standard 1149.1 scan system.
I/O
Device Clock Pins
CLK32K_IN
P13
N9
32-kHz clock input. Digital CMOS 32-kHz clock input driven by an external
32-kHz oscillator if the internal 32-kHz oscillator is not used.
I
CLK32K_OUT
Y12
N10
32-kHz clock output. Clock output reflecting the internal 32-kHz clock.
O
CLK32K_CTRL
AA20
T15
32-kHz clock selection control input. CLK32K_CTRL selects whether or not the
internal 32-kHz oscillator is used or if the 32-kHz clock is to be provided externally
via the CLK32K_IN input. If CLK32K_CTRL is high, the 32-kHz internal oscillator
is used; if CLK32K_CTRL is low, the CMOS input CLK32K_IN is used as a 32-kHz
clock source.
I
OSC32K_IN
W12
T10
32-kHz crystal XI connection. Analog clock input to 32-kHz oscillator for use with
external crystal.
analog
OSC32K_OUT
R12
T9
32-kHz crystal XO connection. Analog output from 32-kHz oscillator for use with
external crystal.
analog
OSC1_IN
Y2
R2
Base crystal XI connection. Analog input to base oscillator for use with external
crystal or to be driven by external 12- or 13-MHz oscillator.
analog
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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