參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 35/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Introduction
23
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
LCD Interface (Continued)
LCD.P[15:0]
D15,
C16,
A17,
G13,
B17,
C17,
D16,
D17,
C18,
B19,
A20,
H13,
G14,
C19,
B21,
D18
D12,
C13,
B12,
F11,
B13,
E12,
A13,
C14,
B14,
A15,
C15,
B15,
A16,
D15,
C16,
B16
LCD pixel data bus. Pixel data is transferred on this output bus to LCD panels.
O
Keyboard Matrix Interface
KB.C[7:0]
V19,
P15,
C20,
C21,
E18,
D19,
D20,
F18
M13,
L12,
A17,
D16,
B17,
E15,
E16,
C17
Keyboard matrix column outputs. KB.Cx column outputs are used in conjunction
with the KB.Rx row inputs to implement a 6x5 or 8x8 keyboard matrix.
O
KB.R[7:0]
M20,
N21,
N19,
E19,
E20,
H14,
F19,
G18
K16,
K17,
K14,
D17,
E17,
F15,
D14,
D13
Keyboard matrix row inputs. KB.Rx row inputs are used in conjunction with the
KB.Cx column outputs to implement a 6x5 or 8x8 keyboard matrix.
I
Multichannel Buffered Serial Ports (McBSPs)
MCBSP1.CLKS
G20
F13
McBSP1 clock source. Provides external clock reference for use with transmitter
or reciever. CLKS is only present on McBSP1.
I
MCBSP1.CLKX
G21
G15
present on all McBSPs. In the case of McBSP1 and McBSP3, the clock input to
the McBSP receiver may also be provided on this terminal via an internal
loop-back connection between the transmitter and receiver clocks.
I/O/Z
MCBSP2.CLKX
Y6
U5
McBSP transmit clock. Serial shift clock reference for the transmitter. CLKX is
MCBSP3.CLKX
W16,
N14
P6,
R16
MCBSP1.FSX
H15,
H18
F17,
F16
McBSP transmit frame sync. Frame synchronization for transmitter. FSX is
input to the McBSP receiver may also be provided on this terminal via an internal
loop-back connection between the transmitter and receiver frame syncs.
I/O/Z
MCBSP2.FSX
W7
T6
present on all McBSPs. In the case of McBSP1 and McBSP3, the frame sync
MCBSP3.FSX
N18,
P18,
P19,
P20
L15,
K12,
K13,
L14
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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