參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 34/160頁
文件大小： 1997K
代理商： OMAP5910(RISC)
Introduction
22
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
EMIFS FLASH and Asynchronous Memory Interface (Continued)
FLASH.A[24:1]
L7,
K3,
K4,
L8,
J1,
J3,
J4,
J2,
K7,
H3,
H4,
K8,
G2,
G3,
G4,
F3,
J7,
E3,
F4,
D2,
E4,
C1,
D3,
J8
J3,
J4,
H6,
H5,
H2,
H4,
H3,
G2,
G1,
G5,
G3,
G4,
E1,
F2,
F4,
F3,
F5,
D2,
E4,
E3,
C2,
C1,
G6,
B1
EMIFS address bus. Address output bus for all EMIFS accesses. FLASH.A[24:1]
provides the upper 24 bits of a 25-bit byte address. The byte enables must be
used to implement 8-bit accesses.
O/Z
FLASH.RDY
H7
C3
EMIFS ready. Active-high ready input used to suspend the EMIFS interface when
the external memory or asynchronous device is not ready to continue the current
cycle.
It is recommended that this pin should be pulled high externally and
unused. See the
OMAP5910 Dual-Core Processor Silicon Errata
(literature
number SPRZ016) for more details.
I
LCD Interface
LCD.VS
D14
D11
LCD vertical sync output. LCD.VS is the frame clock which signals the start of a
new frame of pixels to the LCD panel. In TFT mode, LCD.VS is the vertical
synchronization signal.
O
LCD.HS
H12
E11
LCD horizontal sync. LCD.HS is the line clock which signals the end of a line of
pixels to the LCD panel. In TFT mode, LCD.HS is the horizontal synchronization
signal.
O
LCD.AC
B15
A11
LCD AC-bias. LCD.AC is used to signal the LCD to switch the polarity of the row
and column power supplies to counteract charge buildup causing DC offset. In
TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the
pixel clock.
O
LCD.PCLK
C15
A12
LCD pixel clock output. Clock output provided to synchronize pixel data to the
LCD panels. In passive mode, LCD.PCLK only transitions when LCD.P[15:0] is
valid. In active mode, LCD.PCLK transitions continuously and LCD.AC is used as
the output enable when LCD.P[15:0] is valid.
O
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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