參數(shù)資料
型號: OMAP5910(RISC)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 47/160頁
文件大?。?/td> 1997K
代理商: OMAP5910(RISC)
Functional Overview
35
August 2002 Revised August 2003
SPRS197B
MPU Public Peripherals (accessible by the MPU and the System DMA)
Multichannel Buffered Serial Port (McBSP)
USB Function interface (optional internal transceiver shared with USB Host interface)
USB Host interface with up to three ports (optional internal transceiver shared with USB Function
interface)
One integrated USB transceiver for either host or Function
Inter-Integrated Circuit (I
2
C) Multi-mode master and slave interface
Microwire serial interface
Camera interface providing connectivity to CMOS image sensors
Up to ten MPU general-purpose I/Os (MPUIOs)
32-kHz timer for use with MPU OS
Pulse-Width Tone (PWT) module for tone generation
Pulse-Width Light (PWL) module for LCD backlight control
Keyboard interface (6 x 5 or 8 x 8 matrix)
Multimedia Card or Secure Digital interface (MMC/SD) also configurable as generic SPI port
Two LED Pulse Generator modules (LPG)
Real-Time Clock module (RTC)
HDQ or 1-Wire Master interface for serial communication to battery management devices
Frame Adjustment Counter (FAC)
MPU/DSP Shared Peripherals (Controlling processor is selected by the MPU)
Four Mailboxes for interprocessor communications
Up to 14 General-Purpose I/O pins with interrupt capability to either processor
Three UARTs (UART3 has SIR mode for IrDA functionality)
Clock/Reset/Power Management modules
Configurable Digital Phase-Locked Loop (DPLL) providing clocks to MPU, DSP, and TC
Dedicated USB DPLL providing clocking to USB modules
Integrated base (12- or 13-MHz) and 32-kHz oscillators utilizing external crystals
Reset, clocking and idle/sleep controls for power management
JTAG and ETM9 interfaces for emulation and debug
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