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參數(shù)資料
| 型號： | NAND02GW4B2CZA1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大小： | 1335K |
| 代理商： | NAND02GW4B2CZA1E |
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NAND01G-B2B, NAND02G-B2C
Device operations
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6.8.4
Cache program error bit (SR1)
The cache program error bit can be used to identify if the previous page (page N-1) has been
successfully programmed or not in a cache program operation. SR1 is set to ’1’ when the
cache program operation has failed to program the previous page (page N-1) correctly. If
SR1 is set to ‘0’ the operation has completed successfully.
The cache program error bit is only valid during cache program operations, during other
operations it is don’t care.
6.8.5
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully. The error
bit SR0, in a cache program operation, indicates a failure on page N.
6.8.6
SR4, SR3 and SR2 are reserved
Table 13.
Status register bits
Bit
Name
Logic level
Definition
SR7
Write protection
'1'
Not protected
'0'
Protected
SR6
Program/ erase/ read
controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
Cache ready/busy
'1'
Cache register ready (cache operation only)
'0'
Cache register busy (cache operation only)
SR5
Program/ erase/ read
controller(1)
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
SR4, SR3, SR2
Reserved
Don’t care
SR1
Cache program error(2)
'1'
Page N-1 failed in cache program operation
'0'
Page N-1 programmed successfully
SR0
Generic error
‘1’
Error – operation failed
‘0’
No Error – operation successful
Cache program error
‘1’
Page N failed in cache program operation
‘0’
Page N programmed successfully
1.
Only valid for cache program operations, for other operations it is same as SR6.
2.
Only valid for cache operations, for other operations it is don’t care.
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