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參數(shù)資料
| 型號： | NAND02GW4B2CZA1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | NAND02GW4B2CZA1E |
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Device operations
NAND01G-B2B, NAND02G-B2C
6.5
Cache program
The cache program operation is used to improve the programming throughput by
programming data using the cache register. The cache program operation can only be used
within one block. The cache register allows new data to be input while the previous data that
was transferred to the page buffer is programmed into the memory array.
The following sequence is required to issue a cache program operation (refer to Figure 13):
1.
First of all the program setup command is issued: one bus cycle to issue the program
setup command then 4 or 5 bus write cycles to input the address (see Table 6 and
Table 7). The data is then input (up to 2112 bytes/1056 words) and loaded into the
cache register
2.
One bus cycle is required to issue the confirm command to start the P/E/R controller
3.
The P/E/R controller then transfers the data to the page buffer. During this the device is
busy for a time of tBLBH5
4.
Once the data is loaded into the page buffer the P/E/R controller programs the data into
the memory array. As soon as the cache registers are empty (after tBLBH5) a new
Cache Program command can be issued, while the internal programming is still
executing.
Once the program operation has started the status register can be read using the Read
Status Register command. During cache program operations SR5 can be read to find out
whether the internal programming is ongoing (SR5 = ‘0’) or has completed (SR5 = ‘1’) while
SR6 indicates whether the cache register is ready to accept new data. If any errors have
been detected on the previous page (Page N-1), the cache program error bit SR1 will be set
to ‘1', while if the error has been detected on page N the error bit SR0 will be set to '1’.
When the next page (Page N) of data is input with the Cache Program command, tBLBH5 is
affected by the pending internal programming. The data will only be transferred from the
cache register to the page buffer when the pending program cycle is finished and the page
buffer is available.
If the system monitors the progress of the operation using only the Ready/Busy signal, the
last page of data must be programmed with the Page Program Confirm command (10h).
If the Cache Program Confirm command (15h) is used instead, status register bit SR5 must
be polled to find out if the last programming is finished before starting any other operations.
Figure 13.
Cache program operation
1.
Up to 64 pages can be programmed in one cache program operation.
2.
tCACHEPG is the program time for the last page + the program time for the (last 1)
th page
(Program command cycle time
+ Last page data loading time).
I/O
RB
Address
Inputs
ai08672
80h
Page
Program
Code
Read Status
Register
Busy
Data
Inputs
15h
Cache
Program
Code
80h
Page
Program
Code
15h
Cache Program
Confirm Code
Busy
Last Page
tBLBH5
(Cache Busy time)
tBLBH5
tCACHEPG
SR0
70h
80h
10h
Page
Program
Confirm Code
Busy
First Page
Second Page
(can be repeated up to 63 times)
Address
Inputs
Data
Inputs
Address
Inputs
Data
Inputs
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