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參數(shù)資料
| 型號(hào)： | MT90220AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device |
| 中文描述： | 八路IMA的/單向物理層設(shè)備 |
| 文件頁(yè)數(shù)： | 82/116頁(yè) |
| 文件大小： | 306K |
| 代理商： | MT90220AL |
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MT90220
74
Address (Hex):
Synchronized access The value in this register is used for internal access to the counter when the
transfer command is issued
Reset Value (Hex):
00
217
Bit #
Type
Description
7:4
R/W
The valid bit combinations are:
1011: UTOPIA Input, counter of all cells for link
1010: UTOPIA Input, counter of Idle cells for link
1001: UTOPIA Input, counter of Unassigned cells for link
1000: UTOPIA Input, counter of cell with HEC error, single or multiple bit error
0111: TX Link, total number of cells,
0110: TX Link, number of Idle/Filler cells,
0101: TX Link, number of Stuff cells,
0100: TX Link, number of ICP cells,
0011: RX Link, total number of cells (or stuff cells),
0010: RX Link, number of Idle/Filler cells,
0001: RX Link, number of cells with HEC errors,
0000: RX Link, number of bad ICP cells.
The valid bit combinations are:
1011: IMA Group 3 when UTOPIA Input counter access
1010: IMA Group 2when UTOPIA Input counter access
1001: IMA Group 1when UTOPIA Input counter access
1000: IMA Group 0when UTOPIA Input counter access
0111: Link 7
0110: Link 6
0101: Link 5
0100: Link 4
0011: Link 3
0010: Link 2
0001: Link 1
0000: Link 0
3:0
R/W
Table 93 - Select Counter Register
Address (Hex):
Synchronized access
Reset Value (Bin):
207
0XX00000
Bit #
Type
Description
7
R/W
Write: 0 for normal operation.
Read: 1 when the transfer is done, 0 when the transfer is pending.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred
when the bit 1:0 are 10.
0 will enable the transfer from the uP to the selected counter.
1 will enable the transfer from the selected counter to the uP.
00: Reserved. Do not use.
01: initiate a read or write of the counter value.
10: initiate a read or write of the IRQ enable counter bit.
11: not used.
6
5
4
3
R/W
R/W
R/W
R/W
2
R/W
1:0
R/W
Table 94 - Counter Transfer Command Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device |
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
| MT9041 | Multiple Output Trunk PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
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