參數(shù)資料
型號(hào): MT90220AL
廠商: Mitel Networks Corporation
英文描述: Octal IMA/UNI PHY Device
中文描述: 八路IMA的/單向物理層設(shè)備
文件頁數(shù): 104/116頁
文件大?。?/td> 306K
代理商: MT90220AL
MT90220
96
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
Figure 33 - CPU Interface Motorola Timing - Write Access
AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
UP_R/W* set-up time to UP_CS*
falling edge
t
WS
1
ns
2
Address and Data set up before
rising edge of UP_CS*
t
SU
4
ns
3
UP_AD and Data hold time after
UP_CS rising edge
t
ADH
0
ns
4
UP_R/W low after rising edge or
UP_CS
t
WH
1
ns
5
UP_CS* high before next UP_CS
low
t
CSH
2
(see Note 1)
cycle
system
clock
UP_CS
Address Valid
UP_AD[9:0]
UP_R/W
Data Valid
UP_D[7:0]
t
su
t
ws
UP_OE
t
adh
t
csh
t
wh
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