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參數(shù)資料
| 型號(hào)： | MT90220AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device |
| 中文描述： | 八路IMA的/單向物理層設(shè)備 |
| 文件頁(yè)數(shù)： | 13/116頁(yè) |
| 文件大小： | 306K |
| 代理商： | MT90220AL |
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MT90220
5
9, 10, 11,
12, 13
RxAddr
[4:0]
I
Receive Address
. Five bit wide true data driven from the ATM to PHY layer to
select the appropriate MT90220. RxAddr[4] is the MSB. Each MT90220 keeps its
address. The value for the Tx and Rx portions of the MT90220 can be different.
Receiver Static Memory Interface Signals (see Note 1)
188, 189,
190, 191,
192, 195,
196,197
sr_d
[7:0]
I/O
Static Memory Data Bus
. Data Bus to exchange data between the MT90220 and
the external static memory.
162, 163,
164, 165,
166, 169,
170, 171,
172, 175,
176, 177,
178, 179,
182, 183,
184, 185,
186
sr_a
[18:0]
O
Static Memory Address Bus
. The signal is used to select an entry in the external
static memory.
187
sr_we
O
Static Memory Read/Not Write
. If low, data is written from the MT90220 to the
memory. If high, data is read from the memory to the MT90220.
198, 199
sr_cs_1, 0
O
Static Memory Chip Control Signal
.
Processor Interface Signals (see Note 2)
44, 45, 46,
47, 48, 49,
50, 51
up_d
[7:0]
I/O
Processor Data Bus
. Data Bus to exchange data between the MT90220 and a
local processor.
55, 56, 57,
58, 59, 60,
61, 62, 63,
64, 65
up_a
[10:0]
I
Processor Address Bus
. They are used to select the internal registers and
memory positions of the MT90220.
41
up_r/w
or
up_wr
I
Processor Read/Not Write. Motorola Mode.
This is an input signal. If low, data is
written from the processor to the MT90220. If high, data is read from the MT90220
to the processor.
Processor Not Write (Intel Mode).
This is an input signal. If low, data is written
from the processor to the MT90220. De-asserting this signal to high will terminate a
write access cycle.
40
up_oe
or
up_rd
I
Output enable Motorola Mode.
This is an input signal. This signal should be tied
to GND for Motorola timing mode.
Processor Not Read (Intel Mode).
This is an input signal. If low, data is read from
the MT90220.
39
up_cs
I
Processor Chip Select
. This is an active low input signal. If this signal is high, the
MT90220 ignores all other signals on its processor bus. If this signal is low, the
MT90220 accepts the signals on its processor bus. De-asserting this signal to high
will terminate an access cycle.
67
up_irq
O
Processor Interrupt Request
. If this signal is low, the MT90220 signals to the
processor that an interrupt condition is pending inside the MT90220. Otherwise no
interrupt is pending inside the MT90220. Open drain signal.
PCM Interface Signals
Pin Description (continued)
Pin #
Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device |
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
| MT9041 | Multiple Output Trunk PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
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