參數(shù)資料
型號： MPC5125YVN400
廠商： Freescale Semiconductor
文件頁數(shù)： 48/94頁
文件大?。?/td> 0K
描述： IC MCU 32BIT E300 324TEPBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC51xx
核心處理器： e300
芯體尺寸： 32-位
速度： 400MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 64
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 324-BBGA
包裝： 托盤
MPC5125 Microcontroller Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
52
4.3.5.1
DDR SDRAM AC Timing Specifications
4.3.5.2
MobileDDR/LPDDR SDRAM AC Timing Specifications
Table 21. DDR SDRAM Timing Specifications
At recommended operating conditions with VDD_IO_MEM of 5%
Parameter
Symbol
Min
Max
Unit Notes SpecID
Clock cycle time, CL = x
tCK
6000
—
ps
A5.1
MCK AC differential crosspoint voltage
VOX-AC (VDD_IO_MEM 0.5)– 0.15 (VDD_IO_MEM 0.5) + 0.15
V
1
NOTES:
1 Measured with clock pin loaded with differential 100
termination resistor.
A5.2
CK HIGH pulse width
tCH
0.47
0.53
tCK
A5.3
CK LOW pulse width
tCL
0.47
0.53
tCK
A5.4
Skew between MCK and DQS transitions
tDQSS
0.25
tCK
2,3
2 Measured with all outputs except the clock loaded with 50
termination resistor to V
DD_IO_MEM/2.
3 All transitions measured at mid-supply (V
DD_IO_MEM/2).
A5.5
Address and control output setup time
relative to MCK rising edge
tOS(base)
tCK/2 – 1000
—
ps
A5.6
Address and control output hold time
relative to MCK rising edge
tOH(base)
tCK/2 – 1000
—
ps
A5.7
DQ and DM output setup time relative to
DQS
tDS1(base)
tCK/4 – 750
—
ps
A5.8
DQ and DM output hold time relative to
DQS
tDH1(base)
tCK/4 – 750
—
ps
A5.9
DQS-DQ skew for DQS and associated
DQ inputs
tDQSQ
– (tCK/4 – 600)
tCK/4 – 600
ps
A5.10
DQS window position related to CAS read
command
tDQSEN
2tCK + 1500
3tCK – 1000
ps 1,2,3,4,
5
4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
5 The window position is given for t
DQSEN = 2.0 tCK (RDLY = 2, HALF DQS DLY = QUART DQS DLY = 0) with CL = 3 DDR
SDRAM device. For other values of tDQSEN, the window position is shifted accordingly.
A5.11
Table 22. MobileDDR/LPDDR SDRAM Timing Specifications
At recommended operating conditions with VDD_IO_MEM of 5%
Parameter
Symbol
Min
Max
Unit Notes SpecID
Clock cycle time, CL = x
tCK
6000
—
ps
A5.1
MCK AC differential crosspoint voltage
VOX-AC (VDD_IO_MEM 0.5) – 0.1 (VDD_IO_MEM 0.5) + 0.1
V
1
A5.2
CK HIGH pulse width
tCH
0.47
0.53
tCK
A5.3
CK LOW pulse width
tCL
0.47
0.53
tCK
A5.4
Skew between MCK and DQS
transitions
tDQSS
0.25
tCK
2,3
A5.5
Address and control output setup time
relative to MCK rising edge
tOS(base)
tCK/2 – 1000
—
ps
A5.6
相關(guān)PDF資料
PDF描述
MPC533CVR40 IC MPU 512K FLASH 40MHZ 388-PBGA
MPC535CZP40 IC MCU 1M FLASH 40MHZ 388-BGA
MPC5534MVM80 MCU 1MB FLASH 80MHZ 208MAPBGA
MPC5553MVR132 MCU 1.5MB FLASH 132MHZ 416-PBGA
MPC555LFMZP40 IC MCU 32BIT 40MHZ 272-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC5125YVN400 制造商:Freescale Semiconductor 功能描述:ICMICROPROCESSOR32-BITCMOSPBGA324PI
MPC5125YVN400R 制造商:Freescale Semiconductor 功能描述:POWERPC EMBEDDED SOC - Tape and Reel
MPC5200 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hardware Specifications
MPC5200B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller
MPC5200B_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*