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參數(shù)資料
| 型號(hào)： | MPC5125YVN400 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 37/94頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT E300 324TEPBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | MPC51xx |
| 核心處理器： | e300 |
| 芯體尺寸： | 32-位 |
| 速度： | 400MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，USB OTG |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 64 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.08 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 324-BBGA |
| 包裝： | 托盤 |
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MPC5125 Microcontroller Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
42
4.1.5
Power Dissipation
Power dissipation of the MPC5125 is caused by three different components:
Dissipation of the internal or core digital logic (supplied by VDD)
Dissipation of the analog circuitry (supplied by AVDD_SPLL and AVDD_CPLL)
Dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO)
Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the
dissipation due to the switching of the IO pins cannot be given in general, but must be calculated for each application case using
the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is
the switching frequency, and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the
MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded.
Eqn. 2
Table 10. Power Dissipation
Core Power Supply (VDD_core)
1
NOTES:
1 Typical core power is measured at V
DD_core = 1.4 V, TJ = 25 C.
Mode
High-Performance
Unit
SpecID
e300 = 400 MHz, CSB = 200 MHz
Operational2
2 Operational power is measured while running an entirely cache-resident program with floating-point
multiplication instructions in parallel with DDR write operation.
620
mW
D5.1
Doze3
580
mW
D5.3
Nap3
235
mW
D5.2
Sleep3
230
mW
D5.4
Deep-sleep4
38
mW
D5.5
RTC Power Supply (VBAT)
Hibernation
20
W
D5.6
PLL/OSC Power Supplies (AVDD_SPLL, AVDD_CPLL, AVDD_OSC_TMPS)
5
Operational
18
mW
D5.7
Deep-sleep
55
W
D5.8
Unloaded I/O Power Supplies (VDD_IO, VDD_IO_MEM)
6
VDD_IO
VDD_IO_MEM
Operational
180
40
mW
D5.9
Deep-sleep
5
1
mW
D5.10
P
IO
P
IOint
N
M
+
CVDD_IO
2
f
=
P
total
P
core
P
analog
P
IO
++
=
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