參數(shù)資料
型號： ML9620GAZ210
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù)： 55/79頁
文件大?。?/td> 449K
代理商： ML9620GAZ210
ML9620 User’s Manual
Chapter 4
MCU Interface
4 – 2
4.2
Serial Interface
Figure 4-1 shows the transfer timing.
Address/data transfers begin when the CS pin is at a ‘L’ level and end when it changes to a ‘H’ level.
Because
the ML9620 has an address increment function, the basic transfer consists of ‘ transfer start address + multiple
data’.
Therefore, to access a nonconsecutive address, the CS must be first pulled to a ‘H’ level, and then the
address set.
Perform address/data transfers LSB first, in 8-bit units.
During a transfer, an interval is necessary between
address and data and between consecutive data transfers.
(Refer to Chapter 5, ‘Electrical Characteristics’, for
interval values.)
Note that the SWAIT signal is only generated during the interval between address and data
transfers.
4.2.1 Data write
Data write operations are performed with the following procedure.
After setting the
CS pin and PRD/SRW pin to ‘L’ levels, input an address to the SDI pin. Synchronized to the
rising edge of synchronous clock SCLK, the ML9620 captures the address in an internal register.
When 8
SCLK clocks are received, the ML9620 loads the address into the internal address counter and waits for data
reception.
Next, input data to the SDI pin.
An internal register captures data in a similar manner to the address capture, at
the rising edge of SCLK.
When 8 bits of data have been captured, the ML9620 writes the data to the message
memory or control register specified by the address that was received previously, and then increments the
address counter by 1.
If data is to be written to consecutive addresses, continue the data transfer.
After all
data has been transferred, set the
CS pin to a ‘H’ level.
4.2.2 Data read
Data read operations are performed with the following procedure.
After setting the
CS pin to a ‘L’ level and the PRD/SRW pin to a ‘H’ level, input an address to the SDI pin in
the same manner as for the data write operation.
When 8 SCLK clocks are received, the ML9620 loads the
address into the internal address counter, reads data from the message memory or control register specified by
the address, latches data into a shift register for data output and increments the address counter.
Then, when
SCLK is input, latched data is output from the SDO pin synchronized to the falling edge of SCLK.
At this time,
the contents of the data input from the SDI pin does not matter.
If there exists remaining data to be read, input
another 8 SCLK clocks.
After all the data at consecutive addresses has been read, set the
CS pin to a ‘H’ level.
If the count value of the lower 4 bits of an address overflows (exceeds XFh), the address increment function will
reset the count value of the lower 4 bits to 0 without changing the upper 4 bits of the address, and will continue
counting.
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